Backport DirectNIC patches to nvidia_stable-11.0 from nvidia_stable-10.0 - #35
Backport DirectNIC patches to nvidia_stable-11.0 from nvidia_stable-10.0#35tdavenvidia wants to merge 6 commits into
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@tdavenvidia Some comments from my review... 9170f9d NVIDIA: SAUCE: hw/arm: GB300 workaround for GPU BAR1 GPA=HPA This patch is missing a pick tag. All of the patches seem to have the pick tags in the wrong order, also the SHAs use an inconsistent format. Please pick with -x -s. Example of how it should flow for a clean picked patch: Example of how it should flow for a patch that required fixup: Some functional findings from Codex review. Codex acknowledged these were present in the patches on the 10.1 branch, but we should review and address them now (if applicable).
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@nvmochs Thank you for the review. I appreciate it. While the functional findings from Codex especially 2, 3 ,4 are valid, we have had never encounter them likely because we wont touch 32bit BAR and ROM BAR path for DirectNIC. Having said that, I am addressing all of the comments and apply the required fix. I will push new changes soon. |
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Sounds good, please ping when this is ready for re-review. Thanks! |
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@nvmochs I already did yesterday, but BORO had some comments which I am replying here: Thanks to BORO's Review of PR #35. Here is my reasoning. I will be pushing changes soon.
-Tushar |
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I pushed the new changes; addressed all BORO review as well as your review comments. Please take a look. |
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@tdavenvidia Some additional review comments... While the provenance now looks consistent, is still not correct. The "new" items (tag, annotation notes if needed, and your sign-off) should come after the existing trailers. So using "NVIDIA: SAUCE: hw/arm: GB200 DirectNIC GPA=HPA” as an example, I would expect to see the provenance trailers look like this: There were several complaints about checkpatch warnings / errors. Some of these existed last time, some are new. If possible, I think we should just address them now so we have "clean" patches. ef7ba6c has an inaccurate backport annotation. Codex stated: Should we catch 0xffff as an invalid value and fail early? |
Nvidia’s next generation GB200 platform has Blackwell GPU and CX8 directly
connected through PCIe Gen6 x16 link. Direct P2P PCIe traffic between GPU
and NIC is possible; however, it requires ATS at its core and Grace CPU
does not support PCIe ATS. GPA=HPA solution removes the need for GPA to
HPA address translation by configuring PCIe BARs in the VM with HPA. It
also enables ACPI PCI DSM by setting ‘preserve_config’ to true to avoid VM
from reconfiguring the PCI BARs during boot.
Here is the example of PCIe topology that shows GPU and CX8 behind the PCIe
Switch:
$ lspci -vt
-[0000:00]---00.0-[01-07]----00.0-[02-07]--+-00.0-[03]--+-00.0 Mellanox Technologies CX8 Family [ConnectX-8]
| \-00.1 Mellanox Technologies CX8 Family [ConnectX-8]
\-03.0-[04-07]----00.0-[05-07]--+-08.0-[06]--
\-0c.0-[07]--
-[0002:00]---00.0-[01-07]----00.0-[02-07]--+-00.0-[03]--+-00.0 Mellanox Technologies CX8 Family [ConnectX-8]
| \-00.1 Mellanox Technologies CX8 Family [ConnectX-8]
\-01.0-[04-07]----00.0-[05-07]--+-08.0-[06]--
\-0c.0-[07]--
-[0005:00]---00.0-[01-0a]----00.0-[02-0a]--+-01.0-[03]--
+-02.0-[04]--
+-03.0-[05]--
+-04.0-[06-07]----00.0-[07]----00.0 ASPEED Technology, Inc. ASPEED Graphics Family
+-05.0-[08]----00.0 Renesas Technology Corp. uPD720201 USB 3.0 Host Controller
+-06.0-[09]----00.0 Intel Corporation I210 Gigabit Network Connection
\-07.0-[0a]--
-[0006:00]---00.0-[01-09]----00.0-[02-09]--+-00.0-[03]--+-00.0 Mellanox Technologies MT43244 BlueField-3 integrated ConnectX-7 network controller
| +-00.1 Mellanox Technologies MT43244 BlueField-3 integrated ConnectX-7 network controller
| \-00.2 Mellanox Technologies MT43244 BlueField-3 SoC Management Interface
\-02.0-[04-09]----00.0-[05-09]--+-00.0-[06]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
+-04.0-[07]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
+-08.0-[08]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
\-0c.0-[09]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
-[0008:00]---00.0-[01-06]----00.0-[02-06]--+-00.0-[03]----00.0 Mellanox Technologies Device 2100
\-03.0-[04-06]----00.0-[05-06]----00.0-[06]----00.0 NVIDIA Corporation Device 2941
-[0009:00]---00.0-[01-06]----00.0-[02-06]--+-00.0-[03]----00.0 Mellanox Technologies Device 2100
\-01.0-[04-06]----00.0-[05-06]----00.0-[06]----00.0 NVIDIA Corporation Device 2941
-[0010:00]---00.0-[01-07]----00.0-[02-07]--+-00.0-[03]--+-00.0 Mellanox Technologies CX8 Family [ConnectX-8]
| \-00.1 Mellanox Technologies CX8 Family [ConnectX-8]
\-03.0-[04-07]----00.0-[05-07]--+-08.0-[06]--
\-0c.0-[07]--
-[0012:00]---00.0-[01-07]----00.0-[02-07]--+-00.0-[03]--+-00.0 Mellanox Technologies CX8 Family [ConnectX-8]
| \-00.1 Mellanox Technologies CX8 Family [ConnectX-8]
\-01.0-[04-07]----00.0-[05-07]--+-08.0-[06]--
\-0c.0-[07]--
-[0015:00]---00.0-[01]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
-[0016:00]---00.0-[01-09]----00.0-[02-09]--+-00.0-[03]--+-00.0 Mellanox Technologies MT43244 BlueField-3 integrated ConnectX-7 network controller
| +-00.1 Mellanox Technologies MT43244 BlueField-3 integrated ConnectX-7 network controller
| \-00.2 Mellanox Technologies MT43244 BlueField-3 SoC Management Interface
\-02.0-[04-09]----00.0-[05-09]--+-00.0-[06]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
+-04.0-[07]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
+-08.0-[08]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
\-0c.0-[09]----00.0 Samsung Electronics Co Ltd NVMe SSD Controller PM9A1/PM9A3/980PRO
-[0018:00]---00.0-[01-06]----00.0-[02-06]--+-00.0-[03]----00.0 Mellanox Technologies Device 2100
\-03.0-[04-06]----00.0-[05-06]----00.0-[06]----00.0 NVIDIA Corporation Device 2941
-[0019:00]---00.0-[01-06]----00.0-[02-06]--+-00.0-[03]----00.0 Mellanox Technologies Device 2100
\-01.0-[04-06]----00.0-[05-06]----00.0-[06]----00.0 NVIDIA Corporation Device 2941
GPA=HPA is expected to work with PCIe topology in the VM that resembles
bare metal. In other words, for P2P PCIe traffic (using GPA=HPA) over Gen6,
CX8 NIC (the DMA-PF) and GPU assigned to VM should be under the same PCIe
switch.
Note: PCIe Switch needs special non-conventional ACS configuration such
that minimal P2P routes needed for GPU Direct RDMA should be allowed.
Signed-off-by: Shanker Donthineni <[email protected]>
Signed-off-by: Tushar Dave <[email protected]>
Signed-off-by: Matthew R. Ochs <[email protected]>
Acked-by: Matthew R. Ochs <[email protected]>
Acked-by: Mitchell Augustin <[email protected]>
Signed-off-by: Matthew R. Ochs <[email protected]>
(backported from commit 31a853d https://github.com/NVIDIA/QEMU/commits/nvidia_stable-10.1)
[tdave: context adjustment in hw/arm/virt-acpi-build.c build_dsdt() due to
VFIO_PCI_BASE renamed to VFIO_PCI_DEVICE and build_dsdt signature change;
context adjustment in include/hw/arm/virt.h due to new fields added in
11.0; added NULL checks for sysfsdev/realpath and a missing break in the
ROM-relocation retry loop, prevent 32-bit prefetchable BARs corruption
per PR review feedback]
Signed-off-by: Tushar Dave <[email protected]>
Grace Blackwell GPU PCIe BAR1 is a real BAR exposed to the VM that can
be used for GPUdirect RDMA [1].
This patch assigns HPA to BAR1 in the VM for the reason mentioned in
the commit 54db2e4a632 ("hw/arm: GB200 DirectNIC GPA=HPA").
This patch also assigns appropriate GPA to GPU BAR2 (exposed to VM with
the same size as BAR 1 that emulates C2C cache coherent address space)
to avoid region conflict in PCI bus resource assignment.
[1]: https://lore.kernel.org/lkml/[email protected]/
Signed-off-by: Tushar Dave <[email protected]>
Signed-off-by: Matthew R. Ochs <[email protected]>
Acked-by: Matthew R. Ochs <[email protected]>
Acked-by: Mitchell Augustin <[email protected]>
Signed-off-by: Matthew R. Ochs <[email protected]>
(backported from commit c332310 https://github.com/NVIDIA/QEMU/commits/nvidia_stable-10.1)
[tdave: GPU BARs in the VM must be aligned to correct size before
checking for overlap — found during validation testing on 7.0 kernel]
Signed-off-by: Tushar Dave <[email protected]>
Similar to GB200, GB300 also requires a workaround to make GPU BAR 1 GPA=HPA. Signed-off-by: Tushar Dave <[email protected]> Acked-by: Matthew R. Ochs <[email protected]> Acked-by: Mitchell Augustin <[email protected]> Signed-off-by: Matthew R. Ochs <[email protected]> (backported from commit 295a738 https://github.com/NVIDIA/QEMU/commits/nvidia_stable-10.1) [tdave: wrapped condition and factored shared vendor-ID check per PR review feedback] Signed-off-by: Tushar Dave <[email protected]>
…e ports When a PASID-capable device is added behind the PCIe downstream port, for example, an Nvidia GPU, the PCIe downstream ports must expose ACS capability otherwise PASID won't get enabled. In addition, the other use case is GPUDirect RDMA using Data Direct that must require special ACS controls at the PCIe downstream ports for P2P communication. Signed-off-by: Tushar Dave <[email protected]> Acked-by: Matthew R. Ochs <[email protected]> Acked-by: Mitchell Augustin <[email protected]> Signed-off-by: Matthew R. Ochs <[email protected]> (backported from commit 69ff099 https://github.com/NVIDIA/QEMU/commits/nvidia_stable-10.1) [tdave: fixed tab indentation on the XIO3130_ACS_OFFSET macro continuation to match QEMU's 4-space convention, per PR review feedback] Signed-off-by: Tushar Dave <[email protected]>
To support P2P on Guest we must expose to the guest OS the actual PCIe topology and configuration as set by the HYP. Otherwise, the behavior is considered as un-defined. It might fail by SW or HW. Extend both root port and downstream port to get acs caps that should match the HYP and use them in the guest. Signed-off-by: Yishai Hadas <[email protected]> Signed-off-by: Tushar Dave <[email protected]> Acked-by: Matthew R. Ochs <[email protected]> Acked-by: Mitchell Augustin <[email protected]> Signed-off-by: Matthew R. Ochs <[email protected]> (backported from commit 78accd6 https://github.com/NVIDIA/QEMU/commits/nvidia_stable-10.1) [tdave: context adjustment in hw/pci-bridge/pcie_root_port.c rp_realize() and rp_props[] due to PCIESlot::disable_acs removed in 11.0; context adjustment in include/hw/pci/pcie.h due to pcie_insert_capability() added in 11.0] Signed-off-by: Tushar Dave <[email protected]>
GPUDirect RDMA using data-direct requires a specific ACS configuration on PCIe Root Ports and Downstream Ports. While ACS can be configured via QEMU's 'acs-caps' property, the guest kernel may overwrite ACS during standard programming. This change blocks all guest writes to the PCIe ACS Control register and preserves QEMU-provided ACS settings across device resets on PCIe Root Ports and Downstream Ports. Signed-off-by: Tushar Dave <[email protected]> Acked-by: Matthew R. Ochs <[email protected]> Acked-by: Mitchell Augustin <[email protected]> Signed-off-by: Matthew R. Ochs <[email protected]> (backported from commit b1bcf26 https://github.com/NVIDIA/QEMU/commits/nvidia_stable-10.1) [tdave: base commit's wmask lockdown check, if (is_downstream and p->acs_caps), treats acs-caps=0 the same as acs-caps never being set, since both are 0; fixed to correctly lock ACS Control read-only when acs-caps=0 is explicitly configured, per PR review feedback] Signed-off-by: Tushar Dave <[email protected]>
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Addressed all the comments from your last review. Trailer order is fixed on all 6 commits — provenance trailers, then (backported from ...), then the [tdave: ...] note, then my sign-off last. The backport annotation on the ACS read-only commit now describes the actual deviation directly instead of naming a symbol that doesn't exist in the source commit. All the checkpatch errors/warnings you listed are cleared, including the over-indented break in hw/arm/virt-acpi-build.c that checkpatch itself didn't catch. On the acs-caps=0xffff question from Codex: the root issue was that acs-caps used a same-width sentinel value (0xFFFF) to represent "not configured," so an explicit acs-caps=0xffff was indistinguishable from the property never being touched — it silently fell through to the unconfigured path instead of being validated. I changed the property to use a custom setter that tracks whether acs-caps was actually set by the user, independent of what value was set, so there's no value collision possible anymore. acs-caps=0xffff (and any value with bits outside the supported ACS mask) is now rejected the same way any other invalid value is — Unsupported ACS capabilities 0x... were supplied. Supported capabilities are 0x5f. An explicit acs-caps=0 is also now correctly distinguished from "not configured" and gets the read-only lockdown as expected. Verified with checkpatch (clean across all 6 commits) and a real build + launch matrix covering every value class — valid subsets, invalid in-range masks, and out-of-16-bit-range inputs (all correctly rejected at parse time now) — on both root ports and downstream ports, plus confirmed the configured value survives a device reset correctly. |
Thanks @tdavenvidia! No further issues from me.
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@shamiali2008 Can you review this series as well? |
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LGTM: |
This PR contains GPA=HPA and ACS changes required for DirectNIC GB300 w/CX8.