bench(marlin): add tile-padding performance

[ZX-ModelCloud]

Summary

• Add a standalone benchmark for explicit 4-bit AWQ and GPTQ Marlin tile padding.
• Compare the padded Marlin wrapper with the first format-matched fallback that builds and passes a dense reference.
• Time the raw pre-padded Marlin call separately so input padding and output slicing overhead remain visible.
• Resolve the physical GPU before importing Torch, enforce initial and pre-timing idle gates, randomize variant order, collect CUDA-event samples over multiple rounds, and report a bootstrap 95% speedup lower confidence bound.
• Emit reproducibility metadata, boundary accuracy checks, live result tables, and optional JSON output.

This PR adds benchmark tooling only. It does not change kernels or runtime routing.

Benchmark results

Speedup is fallback latency / padded Marlin latency, so values above 1.0 favor padded Marlin.

The main GPTQ run used one Ampere sm80 GPU with 124 SMs, 4-bit symmetric GPTQ, group size 32, K=4128, N=4096, ExLlama v2 as the correctness-checked fallback, FP16 and BF16, 10 warmups, 30 samples per round, 3 rounds, and 1,000 bootstrap samples.

M	FP16 speedup	FP16 LCB95	BF16 speedup	BF16 LCB95
1	0.520x	0.510x	0.812x	0.804x
512	1.096x	1.083x	1.255x	1.248x
1024	0.951x	0.951x	1.093x	1.093x
8192	0.693x	0.652x	0.842x	0.848x

Additional boundary measurements showed the same mixed behavior:

• AWQ N-tail, K=256, N=200, versus AWQ Triton: LCB95 was 2.123x at M=1 and 1.676x at M=33.
• AWQ K-tail, K=160, N=256, versus native AWQ GEMM: LCB95 was 0.932x at M=1 and 1.220x at M=33.
• GPTQ K-tail, K=160, N=256, versus ExLlama v2: LCB95 was 0.513x at M=1 and 0.554x at M=33.

All reported candidates, raw padded kernel calls, and selected fallbacks passed their dense-reference accuracy checks. For the 4K GPTQ run, padded Marlin maximum absolute error was at most 0.00390625 for FP16 and 0.03125 for BF16.

These are synthetic single-projection measurements from one GPU configuration, not end-to-end model results. The performance run was captured on public commit c50bcfeda with the exact benchmark script included by this PR.

Current routing policy

The results do not support broad automatic routing for tile-misaligned shapes:

• M=1 must have LCB95 at least 1.00x so decode does not regress.
• M greater than 1 must have LCB95 at least 1.05x.
• A local pass is not promotion-ready until it is reproduced on additional GPU configurations.
• Tile-misaligned GPTQ and AWQ shapes therefore remain explicit-backend opt-in. AUTO continues to use the existing fallback.
• A future automatic route should use validated shape and hardware-specific evidence instead of treating an isolated passing M value as an interval.

The JSON report records these gates and leaves promotion_ready false until cross-GPU evidence exists.

Validation

ruff check --no-cache scripts/benchmark_marlin_tile_padding.py
ruff format --check scripts/benchmark_marlin_tile_padding.py
python scripts/benchmark_marlin_tile_padding.py --quick --list-cases
git diff --check

Representative performance command:

CUDA_VISIBLE_DEVICES=GPU_UUID python scripts/benchmark_marlin_tile_padding.py \
  --physical-gpu GPU_UUID --device 0 --quant-method gptq --dtype both \
  --case-pattern ^k_tail_4k$ --m-values 1,512,1024,8192 \
  --warmup 10 --iters 30 --rounds 3 --bootstrap-samples 1000