Skip to content
View Jordan-Leis's full-sized avatar
📚
Studying!!!
📚
Studying!!!

Highlights

  • Pro

Block or report Jordan-Leis

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Content in all repositories owned by your account will be closed.
Maximum 250 characters. Please don’t include any personal information such as legal names or email addresses. Markdown is supported. This note will only be visible to you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
Jordan-Leis/README.md
Hi, I'm Jordan. Hardware, ML, research, and software engineer at Waterloo.

whoami

Jordan's neofetch: Waterloo Electrical Engineering, RTL on Zynq UltraScale+, public GitHub stats, and FPGA / RTL co-op search for 2027.

cat contact.json

{
  "looking_for": "FPGA / RTL co-op, 2027",
  "where": "Asia, Jan–Apr 2027 (Cansbridge Fellowship)",
  "email": "[email protected]",
  "linkedin": "linkedin.com/in/jordan-leis",
  "site": "jordanleis.com",
  "resume": "https://drive.google.com/file/d/1jHbSPjZX3hLAVGLmC30Kj_MwDdtXkR9Z/view?usp=sharing"
}

Email · LinkedIn · Website · Résumé

Pinned Loading

  1. Personal_Website Personal_Website Public

    JordanLeis.com more like TheBomb.com

    JavaScript 1

  2. ScienceGPTstream2/SummarizationTool ScienceGPTstream2/SummarizationTool Public

    Summarization Tool for Science-GPT Project

    TypeScript 6 2

  3. Microgrid-RL Microgrid-RL Public

    Benchmarking deep reinforcement learning algorithms for autonomous energy management in off-grid solar + battery + diesel hybrid microgrids across sub-Saharan Africa.

    Python 5 4

  4. mvm-in-system-verilog mvm-in-system-verilog Public

    Pipelined 128-lane matrix-vector multiplication (MVM) engine in SystemVerilog

    SystemVerilog

  5. tanh-in-system-verilog tanh-in-system-verilog Public

    Fully pipelined fixed-point tanh(x) accelerator in SystemVerilog, 840 MHz Fmax on DSP48E2

    SystemVerilog

  6. morse-code-in-riscv-assembly morse-code-in-riscv-assembly Public

    ASCII-to-Morse LED blinker in bare-metal RISC-V assembly on the SiFive HiFive1

    Assembly