Pinned Loading

1. rv32i-cpu rv32i-cpu Public

   Five-stage SystemVerilog RV32I CPU with forwarding, hazard handling, Spike differential verification, and synthesis/STA tradeoff analysis.

   SystemVerilog

2. rtl-line-codec rtl-line-codec Public

   FPGA-oriented SystemVerilog TX/RX pipeline with NRZ line coding, framing, and Nexys A7 hardware validation.

   SystemVerilog 1

3. async-fifo-cdc async-fifo-cdc Public

   Dual-clock asynchronous FIFO with Gray-code pointers, CDC synchronizers, reset-domain handling, and 1,200-seed verification.

   SystemVerilog

4. pipelined-mac-sta pipelined-mac-sta Public

   Three multiply-accumulate (MAC) architectures compared using Yosys synthesis and OpenSTA timing analysis to evaluate the effects of pipelining on timing, area, and latency.

   SystemVerilog

5. ready-valid-rtl ready-valid-rtl Public

   Parameterized ready/valid buffer and synchronous FIFO with assertions, scoreboards, randomized verification, and synthesis.

   SystemVerilog