Move gate recognition into halfphi, with block seeds as caller-supplied data

[isenbek]

NMOS builds static logic exactly one way: a pullup holds a node high and a
pulldown network to ground beats it, so every static gate is an inverted sum of
products. Parallel transistors are the ORs, series are the ANDs. There is no AND
gate and no OR gate on a die of this era.

That recognition rule is pure structure and belongs here. It currently lives in
tinymachines/6502 as crates/v6502-netlist/src/schematic.rs (516 lines), where
it was measured to contain one literal naming a signal on that die.

Also in scope

blocks.rs in that repo grows functional blocks from a table of seed names. The
table is genuinely 6502-specific (49 chip-named literals) — but the growth
rules are not. Moving the algorithm and taking the seed table as a caller
supplied input is what makes the analysis general, and it is the single largest
remaining chip-specificity in the workspace.

Growth rules worth preserving verbatim, each of which was paid for:

• Growth follows terminals, never gates. A node gated by a decode line is being
  told what to do by the decoder, which is the opposite of belonging to it;
  following gates lets the PLA swallow the chip in three rounds.
• A switch is filed by its channel, not its gate.
• Traversal records power rails but never crosses them.

Why it is worth doing

Running gate recognition over the Z80's 6813 transistors is a measurement nobody
has made. On the 6502 it resolves all but one node; whether that holds on a die
twice the size, and on one from a different design team, is the kind of question
this library exists to make askable.

Acceptance

• Nothing in src/ names a chip.
• The 6502 result is unchanged: 534 inverters, 354 NORs, 39 NANDs, 91 AOI, one
  unresolved node. That downstream repo checks it, so a regression is visible.
• The Z80 and 6800 results are reported, whatever they turn out to be.