diff --git a/PCB/v2.x/README.md b/PCB/v2.x/README.md
index b70feb8..6e7b3ad 100644
--- a/PCB/v2.x/README.md
+++ b/PCB/v2.x/README.md
@@ -108,7 +108,7 @@ The droids use XBee Zigbee 3.0, so the controller joins that network through the
 Recommended bringup order:
 1. Current-limited supply on VSYS, with no carrier fitted: press power for 1 s, then check 3V3 and idle current.
 2. Flash over USB with no button held, with SW_BOOT1 held at power-on if the chip does not enumerate. Confirm `PWR_HOLD` reads high.
-3. Time the shortest press that stays on, at 3.3 V and 4.2 V. The simulation gives under 0.3 s at worst, so a 1 s press is well clear. Run a USB upload with no button held, then confirm a watchdog reset reboots the board. Power off at least 20 times, on USB and on battery, and scope `PWR_EN` and `PWR_LATCH_G`: the board must stay off every time, since the simulation's margin has not been measured.
+3. Time the shortest press that stays on, at 3.3 V and 4.2 V. The simulation gives under 0.4 s at worst, so a 1 s press is well clear. Run a USB upload with no button held, then confirm a watchdog reset reboots the board. Power off at least 20 times, on USB and on battery, and scope `PWR_EN` and `PWR_LATCH_G`: the board must stay off every time, since the simulation's margin has not been measured.
 4. OLED and ICM-42670-P on I2C.
 5. SK6812 RGB LED.
 6. Buttons, using the pin table.
@@ -123,7 +123,7 @@ Recommended bringup order:
 - Battery → bq25185 (charger and power path, 4.2V, 500mA) → TLV62569 (3.3V buck) → 3V3 for everything, including the carrier.
 - Power switch: soft latch (AO3401A PFET + AO3400A NFET) controls the TLV62569 EN pin. USB does not hold it on.
 - Boot: press the power button for about a second → latch enables 3V3 → RXD0's pull-up holds the latch through D_OR2 as soon as the chip has power → firmware drives RXD0 high.
-- Shutdown: firmware sees a hold on IO21 → graceful shutdown → RXD0 low → the gate decays through R_LATCH_G1 → C_LATCH_FB1 kicks it clear of threshold as PWR_EN falls → power cut after about 0.6-2 s, counted from release if the button is still held.
+- Shutdown: firmware sees a hold on IO21 → graceful shutdown → RXD0 low → the gate decays through R_LATCH_G1 → C_LATCH_FB1 kicks it clear of threshold as PWR_EN falls → power cut after about 0.8-2.6 s, counted from release if the button is still held.
 - bq25185 STAT1 and STAT2 go to IO15 and IO14 (open drain, 10kΩ pull-ups to 3V3).
 - Battery voltage: VSYS through R_VSYS1/R_VSYS2 to IO7, reading VSYS/3.
 - Below about 3.3 V on the battery the buck passes it through, and the DRV5055's minimum is 3.0 V, so the firmware cutoff should sit above that.
diff --git a/PCB/v2.x/diagrams/power_control_layout.md b/PCB/v2.x/diagrams/power_control_layout.md
index 0862e9f..dd52a70 100644
--- a/PCB/v2.x/diagrams/power_control_layout.md
+++ b/PCB/v2.x/diagrams/power_control_layout.md
@@ -19,7 +19,7 @@ A press-to-start, software-held latch: the button turns the board on, the MCU ha
 | R_GATE1 | 100kΩ | 0402 | Q_PWR1 gate pull-up — off by default |
 | R_LATCH_G1 | 1MΩ | 0402 | Q_LATCH1 gate pull-down — off by default; sized to not starve the diode-OR's drive (callout D) |
 | C_LATCH_G1 | 1µF | 0402 | Latch-gate filter — keeps the ~2ms battery-insertion transient from lifting `PWR_LATCH_G` (callout I) |
-| C_LATCH_FB1 | 470nF | 0603 | `PWR_EN` to `PWR_LATCH_G` — gives the latch hysteresis at power-off (callout J) |
+| C_LATCH_FB1 | 1µF | 0603 | `PWR_EN` to `PWR_LATCH_G` — gives the latch hysteresis at power-off (callout J) |
 | R_BTN_PU1 | 100kΩ | 0402 | Button sense pull-up to **3V3** (not VSYS) — MCU reads pressed (0V) vs idle (3.3V); callout H |
 | R_INV_BASE1 | 100kΩ | 0402 | Dedicated VSYS pull-up for Q_INV1's base — decoupled from `PWR_BTN_SENSE` (callout F) |
 | D_INV_ISO1 | BAT54W-7-F | SOT-323 | Schottky isolator: lets a press pull Q_INV1's base low without loading `PWR_BTN_SENSE` |
diff --git a/PCB/v2.x/production/bom/snips_controller-bom.csv b/PCB/v2.x/production/bom/snips_controller-bom.csv
index b441eae..8388af9 100644
--- a/PCB/v2.x/production/bom/snips_controller-bom.csv
+++ b/PCB/v2.x/production/bom/snips_controller-bom.csv
@@ -10,7 +10,7 @@ Refs,Quantity,Value,Footprint,MF,MPN,LCSC,Mouser,DigiKey,Hand,DNP
 "R_LATCH_G1","1","1MΩ ±1% 62.5mW | 0402WGF1004TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF1004TCE","C26083","","","",""
 "D_OR1,D_OR2","2","1N4148W switching diode 75V 150mA | 1N4148W | ST | SOD-123","Diode_SMD:D_SOD-123","ST(Semtech)","1N4148W","C81598","","","",""
 "R_TRIG1","1","1kΩ ±1% 62.5mW | 0402WGF1001TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF1001TCE","C11702","","","",""
-"C_EN1,C_OLED_1","2","1µF 50V X5R ±10% | CL10A105KB8NNNC | Samsung | 0603","Capacitor_SMD:C_0603_1608Metric","Samsung Electro-Mechanics","CL10A105KB8NNNC","C15849","","","",""
+"C_EN1,C_LATCH_FB1,C_OLED_1","3","1µF 50V X5R ±10% | CL10A105KB8NNNC | Samsung | 0603","Capacitor_SMD:C_0603_1608Metric","Samsung Electro-Mechanics","CL10A105KB8NNNC","C15849","","","",""
 "C_LATCH_G1","1","1µF 6.3V X5R ±10% | CL05A105KQ5NNNC | Samsung | 0402","Capacitor_SMD:C_0402_1005Metric","Samsung Electro-Mechanics","CL05A105KQ5NNNC","C107372","","","",""
 "C_IMU_2","1","2.2µF 10V X7R ±10% | CL10B225KP8NNNC | Samsung | 0603","Capacitor_SMD:C_0603_1608Metric","Samsung Electro-Mechanics","CL10B225KP8NNNC","C100082","","","",""
 "L_BUCK1","1","2.2µH ±20% 2.9A 44mΩ power inductor | SRN4018-2R2M | Bourns | SMD 4x4mm","Inductor_SMD:L_Bourns-SRN4018","Bourns","SRN4018-2R2M","C913207","","","",""
@@ -22,7 +22,6 @@ Refs,Quantity,Value,Footprint,MF,MPN,LCSC,Mouser,DigiKey,Hand,DNP
 "R_USB_DM1,R_USB_DP1","2","27Ω ±1% 62.5mW | RC0402FR-0727RL | Yageo | 0402","Resistor_SMD:R_0402_1005Metric","Yageo","RC0402FR-0727RL","C138021","","","",""
 "C_MCU_3","1","39pF 50V NP0 ±5% | CC0402JRNPO9BN390 | Yageo | 0402","Capacitor_SMD:C_0402_1005Metric","Yageo","CC0402JRNPO9BN390","C106223","","","",""
 "R_I2C_SCL1,R_I2C_SDA1","2","4.7kΩ ±1% 62.5mW | 0402WGF4701TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF4701TCE","C25900","","","",""
-"C_LATCH_FB1","1","470nF 25V X7R ±10% | CL10B474KA8NNNC | Samsung | 0603","Capacitor_SMD:C_0603_1608Metric","Samsung Electro-Mechanics","CL10B474KA8NNNC","C1623","","","",""
 "R_RGB1","1","470Ω ±1% 62.5mW | 0402WGF4700TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF4700TCE","C25117","","","",""
 "R_CC1,R_CC2","2","5.1kΩ ±1% 62.5mW | 0402WGF5101TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF5101TCE","C25905","","","",""
 "R_FB2","1","56.2kΩ ±1% 62.5mW | RC0402FR-0756K2L | Yageo | 0402","Resistor_SMD:R_0402_1005Metric","Yageo","RC0402FR-0756K2L","C183355","","","",""
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
index c38cda8..6a7cf07 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L4,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
index 8eb54ce..fd6a7eb 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Soldermask,Bot*%
 %TF.FilePolarity,Negative*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
index 2a2a8f7..0a916c7 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Paste,Bot*%
 %TF.FilePolarity,Positive*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
index 16a1fcd..a653043 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Legend,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr b/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
index 850be29..9c763d9 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
@@ -1,11 +1,11 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Profile,NP*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
index 41ec00d..ba26292 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L1,Top*%
 %TF.FilePolarity,Positive*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
index e49bb7f..cc5b205 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Soldermask,Top*%
 %TF.FilePolarity,Negative*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
index ffdd2b1..bc716eb 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
index 7f9b1bf..3d7928c 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
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 %TF.FilePolarity,Positive*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
index dfee322..31ff99c 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
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 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L2,Inr*%
 %TF.FilePolarity,Positive*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
index b82f2c1..bd5f954 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:16-08:00*%
+%TF.CreationDate,2026-11-01T19:51:01-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
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 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:01*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl b/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
index 7ed3fcb..4a45b5b 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
+++ b/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
@@ -1,7 +1,7 @@
 M48
-; DRILL file KiCad 10.0.5 date 2026-11-01T11:55:16
+; DRILL file KiCad 10.0.5 date 2026-11-01T19:51:01
 ; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-11-01T11:55:16-08:00
+; #@! TF.CreationDate,2026-11-01T19:51:01-08:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
 ; #@! TF.FileFunction,NonPlated,1,4,NPTH
 FMAT,2
diff --git a/PCB/v2.x/production/gerbers/snips_controller-PTH.drl b/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
index 4766430..dd2f103 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
+++ b/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
@@ -1,7 +1,7 @@
 M48
-; DRILL file KiCad 10.0.5 date 2026-11-01T11:55:16
+; DRILL file KiCad 10.0.5 date 2026-11-01T19:51:01
 ; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-11-01T11:55:16-08:00
+; #@! TF.CreationDate,2026-11-01T19:51:01-08:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
 ; #@! TF.FileFunction,Plated,1,4,PTH
 FMAT,2
diff --git a/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob b/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
index 486f80a..7c4772b 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
+++ b/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
@@ -5,7 +5,7 @@
       "Application": "Pcbnew",
       "Version": "10.0.5"
     },
-    "CreationDate": "2026-11-01T11:55:16-08:00"
+    "CreationDate": "2026-11-01T19:51:01-08:00"
   },
   "GeneralSpecs": {
     "ProjectId": {
diff --git a/PCB/v2.x/production/gerbers/snips_controller.zip b/PCB/v2.x/production/gerbers/snips_controller.zip
index 0819e6c..e3783ae 100644
Binary files a/PCB/v2.x/production/gerbers/snips_controller.zip and b/PCB/v2.x/production/gerbers/snips_controller.zip differ
diff --git a/PCB/v2.x/production/jlcpcb/Snips_2_0.zip b/PCB/v2.x/production/jlcpcb/Snips_2_0.zip
index c9a92bc..ddad720 100644
Binary files a/PCB/v2.x/production/jlcpcb/Snips_2_0.zip and b/PCB/v2.x/production/jlcpcb/Snips_2_0.zip differ
diff --git a/PCB/v2.x/production/placement/snips_controller-all.pos b/PCB/v2.x/production/placement/snips_controller-all.pos
index 31682f8..46b1566 100644
--- a/PCB/v2.x/production/placement/snips_controller-all.pos
+++ b/PCB/v2.x/production/placement/snips_controller-all.pos
@@ -1,4 +1,4 @@
-### Footprint positions - created on 2026-11-01T11:55:16 ###
+### Footprint positions - created on 2026-11-01T19:51:01 ###
 ### Printed by KiCad version 10.0.5
 ## Unit = mm, Angle = deg.
 ## Side : All
@@ -11,7 +11,7 @@ C_HALL1       100nF_16V_X7R_±10%_|_CL05B104KO5NNNC_|_Samsung_|_0402
 C_IMU_1       100nF_16V_X7R_±10%_|_CL05B104KO5NNNC_|_Samsung_|_0402                                                                                        C_0402_1005Metric                                  127.2000  -125.9000    0.0000  bottom
 C_IMU_2       2.2µF_10V_X7R_±10%_|_CL10B225KP8NNNC_|_Samsung_|_0603                                                                                        C_0603_1608Metric                                  124.7000  -125.7000  180.0000  bottom
 C_IMU_3       10nF_50V_X7R_±10%_|_CL05B103KB5NNNC_|_Samsung_|_0402                                                                                         C_0402_1005Metric                                  127.1800  -128.5000  180.0000  bottom
-C_LATCH_FB1   470nF_25V_X7R_±10%_|_CL10B474KA8NNNC_|_Samsung_|_0603                                                                                        C_0603_1608Metric                                  137.4000   -80.8000  180.0000  bottom
+C_LATCH_FB1   1µF_50V_X5R_±10%_|_CL10A105KB8NNNC_|_Samsung_|_0603                                                                                          C_0603_1608Metric                                  137.4000   -80.8000  180.0000  bottom
 C_LATCH_G1    1µF_6.3V_X5R_±10%_|_CL05A105KQ5NNNC_|_Samsung_|_0402                                                                                         C_0402_1005Metric                                  135.0050   -74.8900  180.0000  bottom
 C_STICK1      100nF_16V_X7R_±10%_|_CL05B104KO5NNNC_|_Samsung_|_0402                                                                                        C_0402_1005Metric                                  145.5050   -76.2050  -90.0000  bottom
 C_SYS_1       10µF_25V_X5R_±10%_|_CL21A106KAYNNNE_|_Samsung_|_0805                                                                                         C_0805_2012Metric                                  134.7000   -94.2500    0.0000  bottom
diff --git a/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr b/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
index afe1842..96387d7 100644
--- a/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
+++ b/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:17-08:00*%
+%TF.CreationDate,2026-11-01T19:51:02-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Component,L4,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:17*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:02*
 %MOMM*%
 %LPD*%
 G01*
@@ -1046,7 +1046,7 @@ X125562500Y-64750000D03*
 D10*
 %TO.C,C_LATCH_FB1*%
 %TO.CFtp,C_0603_1608Metric*%
-%TO.CVal,470nF 25V X7R ±10\u0025 | CL10B474KA8NNNC | Samsung | 0603*%
+%TO.CVal,1µF 50V X5R ±10\u0025 | CL10A105KB8NNNC | Samsung | 0603*%
 %TO.CMnt,SMD*%
 %TO.CRot,0*%
 X137400000Y-80800000D03*
diff --git a/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr b/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
index 8e49eb7..37ba341 100644
--- a/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
+++ b/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:55:17-08:00*%
+%TF.CreationDate,2026-11-01T19:51:02-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Component,L1,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:17*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 19:51:02*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/snips_controller.kicad_pcb b/PCB/v2.x/snips_controller.kicad_pcb
index 7fc390e..bda5006 100644
--- a/PCB/v2.x/snips_controller.kicad_pcb
+++ b/PCB/v2.x/snips_controller.kicad_pcb
@@ -257,7 +257,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:86"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:87"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -1502,7 +1502,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:82"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:83"
 			(at -2 0 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -1882,7 +1882,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:112"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:113"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -2158,7 +2158,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:84"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:85"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -2758,7 +2758,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:77"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:78"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -2961,7 +2961,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:91"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:92"
 			(at 2 0 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -3407,7 +3407,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:88"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:89"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -3779,7 +3779,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:85"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:86"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -4151,7 +4151,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:83"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:84"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -4852,7 +4852,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:115"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:116"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -5725,7 +5725,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:104"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:105"
 			(at 0 -2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -6589,7 +6589,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:93"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:94"
 			(at -2 0 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -8291,7 +8291,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:73"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:74"
 			(at -2 0 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -8607,7 +8607,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:80"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:81"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -8824,7 +8824,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:109"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:110"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -9027,7 +9027,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:90"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:91"
 			(at 2 0 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -9920,7 +9920,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:108"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:109"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -10123,7 +10123,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:94"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:95"
 			(at -2 0 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -10633,7 +10633,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:81"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:82"
 			(at 0 -2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -10845,7 +10845,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:89"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:90"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -11406,7 +11406,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:78"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:79"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -11606,7 +11606,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:87"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:88"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -18497,7 +18497,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:114"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:115"
 			(at 0 -2 90)
 			(layer "B.SilkS")
 			(hide yes)
@@ -19583,7 +19583,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:68"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:69"
 			(at 0 -2 0)
 			(layer "B.SilkS")
 			(hide yes)
@@ -19804,7 +19804,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:92"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:93"
 			(at 0 2 0)
 			(layer "B.SilkS")
 			(hide yes)
@@ -20271,7 +20271,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:69"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:70"
 			(at -2 0 0)
 			(layer "B.SilkS")
 			(hide yes)
@@ -22182,7 +22182,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:96"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:97"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -22985,7 +22985,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:75"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:76"
 			(at 0 2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -24055,7 +24055,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:71"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:72"
 			(at -2 0 270)
 			(layer "B.SilkS")
 			(hide yes)
@@ -24487,7 +24487,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:79"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:80"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -24934,7 +24934,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:74"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:75"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -25150,7 +25150,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:70"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:71"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -25785,7 +25785,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:107"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:108"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -26206,7 +26206,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:95"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:96"
 			(at -2 0 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -27472,7 +27472,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:113"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:114"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -27809,7 +27809,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Value" "470nF 25V X7R ±10% | CL10B474KA8NNNC | Samsung | 0603"
+		(property "Value" "1µF 50V X5R ±10% | CL10A105KB8NNNC | Samsung | 0603"
 			(at 0 -1.43 0)
 			(layer "B.Fab")
 			(uuid "36557735-6d4f-49c3-8576-f9ec90382a28")
@@ -27858,7 +27858,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Voltage" "25V"
+		(property "Voltage" "50V"
 			(at 0 -2 0)
 			(layer "B.SilkS")
 			(hide yes)
@@ -27884,7 +27884,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Manufacturer_Part_Number" "CL10B474KA8NNNC"
+		(property "Manufacturer_Part_Number" "CL10A105KB8NNNC"
 			(at 0 -2 0)
 			(layer "B.SilkS")
 			(hide yes)
@@ -27897,7 +27897,7 @@
 				(justify mirror)
 			)
 		)
-		(property "LCSC" "C1623"
+		(property "LCSC" "C15849"
 			(at 0 -2 0)
 			(layer "B.SilkS")
 			(hide yes)
@@ -27923,7 +27923,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:67"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:68"
 			(at 0 -2 0)
 			(layer "B.SilkS")
 			(hide yes)
@@ -28622,7 +28622,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:111"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:112"
 			(at 0 -2 270)
 			(layer "B.SilkS")
 			(hide yes)
@@ -28830,7 +28830,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:76"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:77"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
diff --git a/PCB/v2.x/stackup/board.kdl b/PCB/v2.x/stackup/board.kdl
index 6d01143..50d139f 100644
--- a/PCB/v2.x/stackup/board.kdl
+++ b/PCB/v2.x/stackup/board.kdl
@@ -63,8 +63,9 @@ design snips_controller {
     place resistor "R_GATE1" designator="R_GATE1" footprint="Resistor_SMD:R_0402_1005Metric" value="100kΩ" bom_value="100kΩ ±1% 62.5mW | 0402WGF1003TCE | UNI-ROYAL | 0402"
     // Gives the latch hysteresis. As PWR_EN falls it kicks the gate down, clear of threshold, so RXD0's pull-up cannot
     // restart the board when it returns at brownout. It also couples a rising gate back into PWR_EN, which is why
-    // R_PWR_EN_PD1 is 22k: at 100k that alone lifts EN past its threshold. See scripts/spice/latch_v2_sim.py.
-    place capacitor "C_LATCH_FB1" designator="C_LATCH_FB1" footprint="Capacitor_SMD:C_0603_1608Metric" value="470nF" bom_value="470nF 25V X7R ±10% | CL10B474KA8NNNC | Samsung | 0603"
+    // R_PWR_EN_PD1 is 22k: at 100k that alone lifts EN past its threshold. It is 1 uF because the XBee carrier adds to the
+    // rail, which collapses more slowly: 470 nF left almost no margin with one fitted. See scripts/spice/latch_v2_sim.py.
+    place capacitor "C_LATCH_FB1" designator="C_LATCH_FB1" footprint="Capacitor_SMD:C_0603_1608Metric" value="1µF" bom_value="1µF 50V X5R ±10% | CL10A105KB8NNNC | Samsung | 0603"
     place resistor "R_INV_BASE1" designator="R_INV_BASE1" footprint="Resistor_SMD:R_0402_1005Metric" value="220kΩ" bom_value="220kΩ ±1% 62.5mW | 0402WGF2203TCE | UNI-ROYAL | 0402"
     place resistor "R_INV_PU1" designator="R_INV_PU1" footprint="Resistor_SMD:R_0402_1005Metric" value="220kΩ" bom_value="220kΩ ±1% 62.5mW | 0402WGF2203TCE | UNI-ROYAL | 0402"
     place resistor "R_ISET1" designator="R_ISET1" footprint="Resistor_SMD:R_0402_1005Metric" value="604Ω" bom_value="604Ω ±1% 62.5mW | AC0402FR-07604RL | Yageo | 0402"
@@ -216,11 +217,6 @@ design snips_controller {
         when footprint="Resistor_SMD:R_0402_1005Metric"
         set mpn="0402WGF2202TCE"
     }
-    match placement {
-        when value="470nF"
-        when footprint="Capacitor_SMD:C_0603_1608Metric"
-        set mpn="CL10B474KA8NNNC"
-    }
     match placement {
         when value="220kΩ"
         when footprint="Resistor_SMD:R_0402_1005Metric"
diff --git a/PCB/v2.x/stackup/purchasing.kdl b/PCB/v2.x/stackup/purchasing.kdl
index e2e22dc..e284d39 100644
--- a/PCB/v2.x/stackup/purchasing.kdl
+++ b/PCB/v2.x/stackup/purchasing.kdl
@@ -173,10 +173,6 @@ mpn "CL05A105KQ5NNNC" manufacturer="Samsung Electro-Mechanics" value="1µF" foot
     catalog lcsc="C107372"
 }
 
-mpn "CL10B474KA8NNNC" manufacturer="Samsung Electro-Mechanics" value="470nF" footprint="Capacitor_SMD:C_0603_1608Metric" rated_voltage="25V" {
-    catalog lcsc="C1623"
-}
-
 mpn "0402WGF2202TCE" manufacturer="UNI-ROYAL(Uniroyal Elec)" value="22kΩ" footprint="Resistor_SMD:R_0402_1005Metric" {
     catalog lcsc="C25768"
 }
diff --git a/scripts/spice/README.md b/scripts/spice/README.md
index a97562b..209add8 100644
--- a/scripts/spice/README.md
+++ b/scripts/spice/README.md
@@ -26,7 +26,7 @@ Set `NGSPICE_LIB` to use a different copy. No Python packages are needed.
 
 ## V2
 
-`latch_v2_sim.py` covers the V2 latch, which differs from V1: C_LATCH_FB1 (470 nF, PWR_EN to gate) gives it hysteresis, R_PWR_EN_PD1 is 22k, C_LATCH_G1 is 1 uF, and R_INV_BASE1 and R_INV_PU1 are 220k. PWR_HOLD is on RXD0, as on V1. It asserts insertion, contact bounce, USB hot-plug, insertion with the pad ESD diodes into the dead rail, the off drain from the resistors, a button knock, press time, a 1 s press holding from the pull-up alone, the hold through an upload, USB pulled while on, power-off with the pull-up returning at 2.0-2.8 V (30k and 100k, 5 and 20 mA), power-off with the button held, and both extremes of the capacitor ratio. Run it with `python3 scripts/spice/latch_v2_sim.py`. It uses a behavioural buck, and the datasheet gives only a typical pull-up, so 30k-100k is a deliberately wide spread. It re-latches the circuit without C_LATCH_FB1 at every load, yet V1 stayed off about 10 of 10 on the bench, so read it as pessimistic.
+`latch_v2_sim.py` covers the V2 latch, which differs from V1: C_LATCH_FB1 (1 uF, PWR_EN to gate) gives it hysteresis, R_PWR_EN_PD1 is 22k, C_LATCH_G1 is 1 uF, and R_INV_BASE1 and R_INV_PU1 are 220k. PWR_HOLD is on RXD0, as on V1. It asserts insertion, contact bounce, USB hot-plug, insertion with the pad ESD diodes into the dead rail, the off drain from the resistors, a button knock, press time, a 1 s press holding from the pull-up alone, the hold through an upload, USB pulled while on, power-off with the pull-up returning at 2.0-2.8 V (30k and 100k, 5 and 20 mA), power-off with the button held, and both extremes of the capacitor ratio. Run it with `python3 scripts/spice/latch_v2_sim.py`. It uses a behavioural buck, and the datasheet gives only a typical pull-up, so 30k-100k is a deliberately wide spread. It re-latches the circuit without C_LATCH_FB1 at every load, yet V1 stayed off about 10 of 10 on the bench, so read it as pessimistic.
 
 ## Keeping it in sync
 
diff --git a/scripts/spice/latch_v2_sim.py b/scripts/spice/latch_v2_sim.py
index 3dafdee..190b237 100755
--- a/scripts/spice/latch_v2_sim.py
+++ b/scripts/spice/latch_v2_sim.py
@@ -34,16 +34,18 @@
 R_INV_BASE1 = R_INV_PU1 = "220k"
 R_PWR_EN_PD1 = "22k"
 C_LATCH_G1 = "1u"
-C_LATCH_FB1 = "470n"
-C_FB_LOW = "230n"     # estimate: a 16 V X7R at 3.5 V bias and -20%, the case with the least kick
+C_LATCH_FB1 = "1u"
+C_FB_LOW = "600n"     # estimate: a 50 V X5R 0603 at 3.5 V bias and -10%, the case with the least kick
+C_FB_HIGH = "1.2u"    # estimate: +10% and a little over, the case with the most kick
+C_RAIL = "48u"        # V2 nominal with the XBee carrier: a heavier rail is the harder case at power-off
 C_LATCH_LOW = "0.55u" # estimate: -10% tolerance and about -40% for a 6.3 V 0402 X5R at 2.8 V bias
 CORNERS = ((3.0, 1.45, 1.3), (3.7, 1.05, 0.9), (4.2, 0.65, 0.6), (4.5, 0.65, 0.6))
 WPU = ("30k", "100k")     # the datasheet gives only 45k typical, so this is a deliberately wide spread
 BROWNOUTS = (2.8, 2.4, 2.0)  # rail level at which the chip resets and the pull-up returns
 
 MAX_GATE_OFF = 0.5    # V, well under the AO3400A's 0.65 V minimum threshold
-MAX_PRESS_S = 0.5     # button press to PWR_EN on
-MAX_OFF_S = 3.0       # PWR_HOLD low to PWR_EN low
+MAX_PRESS_S = 0.6     # button press to PWR_EN on
+MAX_OFF_S = 4.0       # PWR_HOLD low to PWR_EN low
 MAX_OFF_DRAIN = 60e-6 # A from VSYS with the board off, resistors only: no IC quiescent current
 BOOT_PRESS_S = 1.0    # press the board must accept as a normal turn-on
 BUMP_S = 0.02         # knock on the button that must not turn the board on
@@ -81,7 +83,7 @@ def core(vthn, vthp, vsys_pwl, sw_pwl, c_latch=C_LATCH_G1, c_fb=C_LATCH_FB1):
 """
 
 
-def buck(vsys, load_a=0.06, c="37u"):
+def buck(vsys, load_a=0.06, c=C_RAIL):
     v = min(3.32, vsys - 0.05)
     return f"V33 bk 0 {v}\nSbk bk v3v3 pwren 0 SWBK\nCrail v3v3 0 {c}\nRload v3v3 0 {v / load_a}\n"
 
@@ -252,7 +254,7 @@ def offheld():
 
 def ratio():
     out = []
-    for name, c_latch, c_fb in (("least kick", "1.1u", C_FB_LOW), ("most kick", C_LATCH_LOW, "560n")):
+    for name, c_latch, c_fb in (("least kick", "1.1u", C_FB_LOW), ("most kick", C_LATCH_LOW, C_FB_HIGH)):
         for v, n, p in CORNERS[:3]:
             fell, low, pk = stays_off(v, n, p, 0.005, "30k", 2.8, c_latch, c_fb)
             ok = fell is not None and low and pk < n