diff --git a/PCB/v2.x/GPIO_table.md b/PCB/v2.x/GPIO_table.md
index b536795..6ca725a 100644
--- a/PCB/v2.x/GPIO_table.md
+++ b/PCB/v2.x/GPIO_table.md
@@ -17,15 +17,15 @@ Pins are chosen by position, not carried over from V1, so V2 needs its own firmw
## Module rules
- **Variant:** use the -N8.
-- **Straps:** IO0 is pulled up by R_BOOT_PU1. IO45 and IO46 are unconnected, so nothing can disturb the boot mode or flash voltage. IO3 carries PWR_HOLD: its strap only selects the JTAG source, which is ignored at default eFuses (Table 3-5).
+- **Straps:** IO0 is pulled up by R_BOOT_PU1. IO3, IO45 and IO46 are unconnected, so nothing can disturb the boot mode or flash voltage.
- **ADC:** analog inputs stay on ADC1 (IO1-IO10), since ADC2 is not usable while the Wi-Fi radio runs, which ESP-NOW needs.
-- **PWR_HOLD is on IO3,** which has no reset pull (ESP32-S3 datasheet Table 2-1). RXD0's pull-up could re-latch the board as the rail collapses at power-off. It has to be an RTC pad (IO0-IO21): on V1 hardware IO3's hold lasted through a full USB upload, while IO42, a digital pad, lost its hold on the USB reset that ends an upload. C_LATCH_G1 (1 µF) carries the latch through a reset of about 300 ms at worst (derated capacitor, flat cell).
-- **Firmware must latch PWR_HOLD with `gpio_hold_en(IO3)` once it has driven it high,** so it survives resets and USB uploads, and must call `gpio_hold_dis(IO3)` before driving it low to power off. Light sleep must not release it. The V1 test ran IO3 with no load, so confirm with a real upload at V2 bring-up.
+- **PWR_HOLD is on RXD0,** whose pull-up at and after reset (ESP32-S3 datasheet Table 2-1) holds the latch through any reset or USB upload with no firmware help. The same pull-up returns as the rail collapses at power-off, so C_LATCH_FB1 gives the latch hysteresis and R_PWR_EN_PD1 is 22 kΩ. `scripts/spice/latch_v2_sim.py` covers this.
+- **Firmware drives RXD0 high early in boot and low to power off,** and must never start UART0 receive on it. Do not use `gpio_hold` for PWR_HOLD: on V1 hardware IO42's hold did not survive the USB reset that ends every upload.
- **Power button sense stays on an RTC-domain pin.** With the board off, VSYS lifts this node through R_INV_BASE1 and D_INV_ISO1. V1 verified that on a VDD3P3_RTC pin; IO33-IO37 are in the VDD_SPI domain (Table 2-1).
- **TXD0 (IO43)** prints the boot log, so it stays free for debugging. RGB data has moved off it, so the LED no longer sees that traffic.
-- **Boot glitches:** the low-level power-up glitches on IO1-IO17 (Table 2-2, where IO15 and IO16 appear as XTAL_32K) are 60 µs. Those pins carry only inputs, except IO1 (SLEEP_RQ, where low means awake) and IO3 (PWR_HOLD, where D_OR2 blocks a low). XBee RESET is on RXD0, which has no listed glitch.
+- **Boot glitches:** the low-level power-up glitches on IO1-IO17 (Table 2-2, where IO15 and IO16 appear as XTAL_32K) are 60 µs. Those pins carry only inputs, except IO1 (SLEEP_RQ, where low means awake). XBee RESET is on IO42, which has no listed glitch.
- **IO26 stays unconnected.** It is the PSRAM chip-select, and Arduino runs a PSRAM probe at every boot, so it is driven before `setup()`. The probe fails on the -N8, which has no PSRAM, and boot continues.
-- **Do not flash V1 firmware on V2.** It would leave PWR_HOLD unheld on IO3, since V1 holds IO44, and treat other V2 pins as SPI. V2 needs its own pin map.
+- **Do not flash V1 firmware on V2.** It would treat V2 pins as SPI and read the wrong buttons. V2 needs its own pin map.
- **EN:** 10 kΩ and 1 µF, as Espressif advises (Peripheral Schematics), so EN crosses 0.75 × VDD about 14 ms after the rail is up. V1 has no capacitor.
- **Pad 61:** the thermal pad is 9 segments, soldered to GND.
@@ -64,8 +64,8 @@ Pins are chosen by position, not carried over from V1, so V2 needs its own firmw
| XBee RTS | IO39 | 35 | Carrier pad 4 |
| Vol down | IO40 | 36 | Direct, active low, internal pull-up |
| XBee ON/SLEEP | IO41 | 37 | Carrier pad 5 |
-| Power hold (PWR_HOLD) | IO3 | 7 | Must go high early in boot, then latched with `gpio_hold_en` |
-| XBee RESET | RXD0 (IO44) | 40 | Carrier pad 6. Drive open drain only: low or released. The pull-up is on the carrier, and RXD0's own pull-up is harmless here |
+| Power hold (PWR_HOLD) | RXD0 (IO44) | 40 | RXD0's pull-up holds it through any reset. Firmware drives it high in boot and low to power off. Never use it as UART0 |
+| XBee RESET | IO42 | 38 | Carrier pad 6. Drive open drain only: low or released. The pull-up is on the carrier |
| Reset | EN | 45 | R_EN_PU1 and C_EN1 only, no button |
Antenna: the module's connector is the W.FL/MHF III size, not standard U.FL. The XBee on the carrier has its own U.FL, so each radio has a separate antenna.
@@ -92,4 +92,4 @@ Every button wires straight to a module GPIO and to GND, using the internal pull
OLED 0x3C, ICM-42670-P 0x68. R_I2C_SDA1 and R_I2C_SCL1 stay on the board so the IMU works with no OLED attached.
## Free pins
-TXD0 (IO43) and IO42 are free. Leave IO26 unconnected (see Module rules). IO45 and IO46 are straps, so leave them unconnected.
+TXD0 (IO43) is free. Leave IO26 unconnected (see Module rules). IO3, IO45 and IO46 are straps, so leave them unconnected.
diff --git a/PCB/v2.x/README.md b/PCB/v2.x/README.md
index 36b2799..b70feb8 100644
--- a/PCB/v2.x/README.md
+++ b/PCB/v2.x/README.md
@@ -15,8 +15,8 @@ through `snips_controller.stackup_sch`; sync it with the Stackup KiCad plugin. R
- **XBee:** optional. U_XBEE1 is a row of 12 hand-solder pads on the bottom for a 22 x 17 mm castellated daughter board, which carries the XBee 3 Micro, its decoupling, the RESET pull-up and RC, and the ATTN/BOOTMODE pull-up. The link is UART with flow control, not SPI. RTS and DTR also allow XBee serial firmware recovery through the ESP32. Leave the area inside the pads free of parts; vias there stay tented. See `GPIO_table.md`.
- **Reflow:** the bottom side goes first and the top side last, because Espressif requires a single reflow for the module (datasheet section 12.3). The XBee reflows on its own carrier and never goes upside down, which is what stopped the two modules from sharing this board before.
- **Radio link:** Amidala's droids use XBee Zigbee 3.0, so a Zigbee controller needs the carrier. The firmware still has to move from the XBee's SPI interface to UART, and needs a V2 pin map.
-- **Programming:** USB, through the module's native USB. To force download mode, hold SW_BOOT1 while pressing the power button. A blank board has no firmware to latch PWR_HOLD, so hold the power button through its first flash. After that, uploads need no button.
-- **No reset button:** the power button can only turn the board on. PWR_HOLD is on IO3, an RTC pad with no reset pull, and C_LATCH_G1 (1 µF) carries the latch through a reset of about 300 ms at worst (derated capacitor, flat cell). Firmware latches the pin with `gpio_hold_en`, so a longer reset or a USB upload holds power with no button, and releases it with `gpio_hold_dis` to power off. Keep a watchdog running to recover from a hang.
+- **Programming:** USB, through the module's native USB. To force download mode, hold SW_BOOT1 while pressing the power button. RXD0's pull-up holds the latch with no firmware, so a blank board flashes after a 1 s press, with no button held during the upload.
+- **No reset button:** the power button turns the board on, and only firmware turns it off. PWR_HOLD is on RXD0, whose pull-up holds the latch through any reset or USB upload, so a blank or hung board stays on until USB and the battery are removed. Keep a watchdog running to recover from a hang. C_LATCH_FB1 gives the latch hysteresis, so that pull-up cannot restart the board at power-off, and R_PWR_EN_PD1 is 22 kΩ so a rising gate cannot couple through it and lift EN.
- **Buttons:** all 13 connect directly to module GPIOs. See `GPIO_table.md`.
- **Power blocks:** the buck, charger and power latch follow V1's relative placement, all on the bottom. Two charger GND vias were moved 0.1-0.75 mm in V1's layout to clear earlier button positions. C_BUCK_IN1 turned 90 degrees with its VSYS pad straight above the VIN pin. BUCK_FB runs around the input cap and hops to F.Cu past the inductor, so both planes shield it; keep it out from under L_BUCK1. The latch is too long to fit whole, so it is split at `PWR_BTN_TRIGGER`: the switch and `PWR_LATCH_G` node sit under the stick, turned 270 degrees, and the inverter sits beside the stick's lower pins. See `diagrams/` for why they are arranged this way.
- **OLED cable:** U_OLED1's opening faces USB, and a Qwiic plug is 7.0 mm wide with its protrusions, so keep top-side parts out of x 0.9-7.9 mm from the mouth at y 52.7 mm down to the MH3 post. Check that a real cable goes in before committing the shell.
@@ -106,9 +106,9 @@ The droids use XBee Zigbee 3.0, so the controller joins that network through the
## Bringup Sequence
Recommended bringup order:
-1. Current-limited supply on VSYS, with no carrier fitted: check 3V3 and idle current with the power button held.
-2. Flash over USB, holding the power button, with SW_BOOT1 held if the chip does not enumerate. Confirm firmware drives `PWR_HOLD` high.
-3. Time the shortest press that stays on, at 3.3 V and 4.2 V. The simulation gives 0.1-0.2 s on a normal cell and up to about 0.4 s on a flat one, set by when firmware drives `PWR_HOLD`, so plan on a half-second press and keep that drive early in boot. Run a USB upload with no button held, which is the first test of IO3's hold under D_OR2's load, then confirm a watchdog reset reboots the board and a graceful shutdown stays off.
+1. Current-limited supply on VSYS, with no carrier fitted: press power for 1 s, then check 3V3 and idle current.
+2. Flash over USB with no button held, with SW_BOOT1 held at power-on if the chip does not enumerate. Confirm `PWR_HOLD` reads high.
+3. Time the shortest press that stays on, at 3.3 V and 4.2 V. The simulation gives under 0.3 s at worst, so a 1 s press is well clear. Run a USB upload with no button held, then confirm a watchdog reset reboots the board. Power off at least 20 times, on USB and on battery, and scope `PWR_EN` and `PWR_LATCH_G`: the board must stay off every time, since the simulation's margin has not been measured.
4. OLED and ICM-42670-P on I2C.
5. SK6812 RGB LED.
6. Buttons, using the pin table.
@@ -122,8 +122,8 @@ Recommended bringup order:
- Battery → bq25185 (charger and power path, 4.2V, 500mA) → TLV62569 (3.3V buck) → 3V3 for everything, including the carrier.
- Power switch: soft latch (AO3401A PFET + AO3400A NFET) controls the TLV62569 EN pin. USB does not hold it on.
-- Boot: press the power button → latch enables 3V3 → module boots → IO3 goes high through D_OR2 to hold the latch, then firmware latches it with `gpio_hold_en`.
-- Shutdown: firmware sees a hold on IO21 → graceful shutdown → `gpio_hold_dis`, IO3 low → the gate decays through R_LATCH_G1 in about 0.6-1.7 s → power cut.
+- Boot: press the power button for about a second → latch enables 3V3 → RXD0's pull-up holds the latch through D_OR2 as soon as the chip has power → firmware drives RXD0 high.
+- Shutdown: firmware sees a hold on IO21 → graceful shutdown → RXD0 low → the gate decays through R_LATCH_G1 → C_LATCH_FB1 kicks it clear of threshold as PWR_EN falls → power cut after about 0.6-2 s, counted from release if the button is still held.
- bq25185 STAT1 and STAT2 go to IO15 and IO14 (open drain, 10kΩ pull-ups to 3V3).
- Battery voltage: VSYS through R_VSYS1/R_VSYS2 to IO7, reading VSYS/3.
- Below about 3.3 V on the battery the buck passes it through, and the DRV5055's minimum is 3.0 V, so the firmware cutoff should sit above that.
diff --git a/PCB/v2.x/diagrams/power_control_layout.md b/PCB/v2.x/diagrams/power_control_layout.md
index ff57b50..0862e9f 100644
--- a/PCB/v2.x/diagrams/power_control_layout.md
+++ b/PCB/v2.x/diagrams/power_control_layout.md
@@ -13,12 +13,13 @@ A press-to-start, software-held latch: the button turns the board on, the MCU ha
| Ref | Value | Footprint | Role |
|---|---|---|---|
| Q_PWR1 | AO3401A | SOT-23 | EN switch — VSYS to PWR_EN, low current |
-| R_PWR_EN_PD1 | 100kΩ | 0402 | `PWR_EN` pull-down to GND — the buck's EN pin has no internal bias and must not be left floating (callout G) |
+| R_PWR_EN_PD1 | 22kΩ | 0402 | `PWR_EN` pull-down to GND — the buck's EN pin has no internal bias and must not be left floating (callout G). 22kΩ, not 100kΩ, so a rising gate cannot couple through C_LATCH_FB1 and lift EN (callout J) |
| Q_LATCH1 | AO3400A | SOT-23 | Pulls Q_PWR1's gate low to turn it on; low-Vth (≤1.45V) so a press still turns it on at the bottom of the battery range (callout D) |
| D_OR1 / D_OR2 | 1N4148W | SOD-123 | Diode-OR: `PWR_BTN_TRIGGER` (actual button press, via the inverter) or MCU hold, either one latches power on |
| R_GATE1 | 100kΩ | 0402 | Q_PWR1 gate pull-up — off by default |
| R_LATCH_G1 | 1MΩ | 0402 | Q_LATCH1 gate pull-down — off by default; sized to not starve the diode-OR's drive (callout D) |
-| C_LATCH_G1 | 100nF | 0402 | Latch-gate filter — keeps the ~2ms battery-insertion transient from lifting `PWR_LATCH_G` (callout I) |
+| C_LATCH_G1 | 1µF | 0402 | Latch-gate filter — keeps the ~2ms battery-insertion transient from lifting `PWR_LATCH_G` (callout I) |
+| C_LATCH_FB1 | 470nF | 0603 | `PWR_EN` to `PWR_LATCH_G` — gives the latch hysteresis at power-off (callout J) |
| R_BTN_PU1 | 100kΩ | 0402 | Button sense pull-up to **3V3** (not VSYS) — MCU reads pressed (0V) vs idle (3.3V); callout H |
| R_INV_BASE1 | 100kΩ | 0402 | Dedicated VSYS pull-up for Q_INV1's base — decoupled from `PWR_BTN_SENSE` (callout F) |
| D_INV_ISO1 | BAT54W-7-F | SOT-323 | Schottky isolator: lets a press pull Q_INV1's base low without loading `PWR_BTN_SENSE` |
@@ -47,11 +48,12 @@ Top copper layer. The VSYS→PWR_EN path runs straight across the top as one thi
| **B** | **SW_PWR1's position isn't yours to optimize electrically.** It has to land under a hole in whatever enclosure this board sits in — mechanical placement drives this part, and the rest of the latch logic has to route to wherever that ends up, not the other way around. |
| **C** | **C_DBNC1 sits right on the switch's own pins.** Same principle as the charger's pushbutton guidance in its own datasheet: the debounce cap does its job by being close to the contact bounce it's filtering, not by being close to anything else. |
| **D** | **The diode-OR and its pull-down are one compact decision node — and R_LATCH_G1's value is load-bearing, not incidental.** D_OR1, D_OR2, R_LATCH_G1, and Q_LATCH1's gate all meet at PWR_LATCH_G. A press only drives this node through `R_INV_PU1` (100kΩ) and a diode drop — with the original 10kΩ pull-down, that divider left barely 0.3V at Q_LATCH1's gate, nowhere near enough to turn it on. Raised to 1MΩ, the same divider delivers ~2.4V at the bottom of the battery range (VSYS≈3.0V, modelling a real ~0.35V diode drop at µA currents) up to ~3.5V at full charge, without adding any idle current (that's set by `R_INV_PU1`, untouched). A 2N7002's worst-case threshold is 2.5V, which left no margin at the bottom, so `Q_LATCH1` is an AO3400A (Vgs(th) ≤1.45V): at least ~1V of overdrive everywhere. Keeping this cluster tight matters less for noise than for just keeping the logic legible on the board. |
-| **E** | **PWR_HOLD arriving late is a hard failure, not a glitch.** Per this project's own GPIO notes, IO3 (PWR_HOLD) must go high as the MCU's very first instruction — release the button before that happens and R_LATCH_G1's pull-down turns everything back off. Not a layout fix, but it's the reason D_OR2's path exists at all. |
+| **E** | **PWR_HOLD has to be up before the button is released.** RXD0 (PWR_HOLD) has a pull-up at and after reset, so it rises as soon as the chip has power, and firmware drives it high in boot — release the button before that happens and R_LATCH_G1's pull-down turns everything back off. Not a layout fix, but it's the reason D_OR2's path exists at all. |
| **F** | **D_OR1 can't read `PWR_BTN_SENSE` directly — found the hard way, on real hardware.** The original design had `R_BTN_PU1` (to VSYS) and a since-removed `R_PWR_SENSE1` (to GND) both on that node, dividing it to roughly half VSYS at idle — comfortably above a diode's ~0.6V forward threshold, so `D_OR1` was forward-biased (and the board powered on) the instant a battery was plugged in, button or no button. The inverter fixes this properly instead of just retuning the divider: idle, `Q_INV1` is on and holds `PWR_BTN_TRIGGER` at GND; pressed, it turns off and `R_INV_PU1` pulls `PWR_BTN_TRIGGER` to VSYS. Only a real press can forward-bias `D_OR1` now. Keep this block close to `D_OR1` — it's parts serving one signal, not worth spreading out.
**Second-order bug, found the same way:** the inverter's own base resistor originally tapped `PWR_BTN_SENSE` directly, in series with `R_BTN_PU1` — stealing enough idle base current to sag the MCU's own button-read node to ~1V instead of near-VSYS. `R_INV_BASE1` is now its own dedicated 100kΩ pull-up straight to VSYS (not sharing current with `R_BTN_PU1`), and `D_INV_ISO1` (a Schottky, chosen specifically for its lower forward drop than Q_INV1's own base-emitter junction) lets a press still pull the base low without ever loading `PWR_BTN_SENSE`. |
| **G** | **`PWR_EN` had no defined rest state — TI's own datasheet says not to do this.** `Q_PWR1`'s drain feeds the buck's EN pin directly, with nothing else on that node. TLV62569's EN pin is a bare comparator input with no internal pull ("Do not leave floating" per its datasheet) — with `Q_PWR1` off, EN was held by MOSFET/input leakage alone, no guaranteed logic level. `R_PWR_EN_PD1` (100kΩ to GND) fixes it: negligible loading when `Q_PWR1`'s tens-of-mΩ RDS(on) is driving EN high, solid GND the instant it's off. |
| **H** | **`PWR_BTN_SENSE` must never sit above the MCU's rail.** It lands directly on IO21 (module pin 25), whose ceiling is VDD + 0.3V (~3.6V), but `R_BTN_PU1` used to pull it to VSYS — up to ~4.5V on USB, and it back-fed the unpowered 3V3 rail through the pin's clamp diode whenever the MCU was off. Since `R_INV_BASE1` gave the inverter its own VSYS pull-up (callout F), `R_BTN_PU1` no longer has to supply the inverter, so it now pulls to 3V3: idle reads 3.3V, and with the MCU off the node is simply unpowered instead of leaking into the rail. |
| **I** | **Battery insertion used to blip `PWR_EN` for ~2ms — found in simulation, since no board existed to bench-test.** When VSYS first appears, `Q_INV1` isn't conducting yet: its base current is diverted through `D_INV_ISO1` into the discharged `C_DBNC1` until that charges to ~0.4V. For that ~1–2ms `PWR_BTN_TRIGGER` follows VSYS, `PWR_LATCH_G` rises to ~VSYS−0.6V, and `Q_PWR1` briefly enables the buck. `C_LATCH_G1` (100nF against the 100kΩ pull-up) makes the gate rise slowly enough that the transient peaks at ~0.3V — well under the AO3400A's minimum threshold — at the cost of 4–8ms of press latency, and it gives release a little extra hold time. Keep it right at `PWR_LATCH_G`. |
+| **J** | **With no hysteresis the latch could restart itself at power-off — found in simulation.** The gate crawls down through threshold, so `PWR_EN` falls with the gate right at the edge, and RXD0's pull-up returns as the rail collapses. `C_LATCH_FB1` kicks the gate clear as `PWR_EN` falls. It also couples a rising gate back into `PWR_EN`, which at 100kΩ lifts EN past its threshold with the capacitors at their tolerance extremes, so `R_PWR_EN_PD1` is 22kΩ. Bigger `C_LATCH_G1`, extra diodes and pull-downs on the hold line do not fix this. |
## Routing priority
@@ -64,7 +66,7 @@ The button's position is fixed by the enclosure before you start — everything
5. Keep R_INV_BASE1, D_INV_ISO1, Q_INV1, and R_INV_PU1 together as their own small block, close to D_OR1 — they're a single-purpose inverter, not independent parts.
6. Bring PWR_BTN_SENSE and PWR_HOLD in from wherever the MCU sheet actually sits — these are off-sheet nets, not local components.
7. Drop `R_PWR_EN_PD1` right at Q_PWR1's drain, on the way to `PWR_EN` leaving the sheet — it's a bias resistor for that pin, not an independent part.
-8. Put `C_LATCH_G1` on the `PWR_LATCH_G` node next to `R_LATCH_G1` and `Q_LATCH1`'s gate, with a short GND return.
+8. Put `C_LATCH_G1` on the `PWR_LATCH_G` node next to `R_LATCH_G1` and `Q_LATCH1`'s gate, with a short GND return. Put `C_LATCH_FB1` beside `Q_PWR1`'s drain, with a short `PWR_EN` connection.
> **Checked, not just assumed:** AO3401A is rated for 4A continuous with <60mΩ RDS(on) at 4.5V gate drive in this SOT-23 package — comfortably oversized for a handheld controller's sub-2A system budget, so this isn't a thermal risk the way the charger's WSON is. MMBT3904 is a general-purpose small-signal part switching microamps here (just enough to bias a diode) — nowhere near its ratings, no thermal consideration needed. BAT54W-7-F's job is purely to isolate two nodes at sub-1V forward drop, also nowhere near its ratings. Connectivity alone (ERC, netlist, DRC) doesn't catch bad DC bias points — the `R_LATCH_G1`/`PWR_BTN_SENSE` loading bugs in callouts D and F, and the floating `PWR_EN` in callout G, all passed every connectivity check and were only found by actually working through the bias/divider math or reading the driven IC's own datasheet, so don't treat a clean ERC/DRC as proof a gate-drive, sense, or enable network will behave.
diff --git a/PCB/v2.x/production/bom/snips_controller-bom.csv b/PCB/v2.x/production/bom/snips_controller-bom.csv
index 8cfb34e..b441eae 100644
--- a/PCB/v2.x/production/bom/snips_controller-bom.csv
+++ b/PCB/v2.x/production/bom/snips_controller-bom.csv
@@ -1,6 +1,6 @@
Refs,Quantity,Value,Footprint,MF,MPN,LCSC,Mouser,DigiKey,Hand,DNP
"U_CHG1","1","1-cell Li-ion charger 1A | BQ25185DLHR | TI | WSON-10","BQ25185DLHR:IC_BQ25185DLHR","Texas Instruments","BQ25185DLHR","C19725033","","","",""
-"R_BTN_PU1,R_GATE1,R_PWR_EN_PD1,R_VSYS2","4","100kΩ ±1% 62.5mW | 0402WGF1003TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF1003TCE","C25741","","","",""
+"R_BTN_PU1,R_GATE1,R_VSYS2","3","100kΩ ±1% 62.5mW | 0402WGF1003TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF1003TCE","C25741","","","",""
"C_DBNC1,C_HALL1,C_IMU_1,C_MCU_2,C_OLED_2,C_RGB1,C_STICK1,C_SYS_2,C_TRIG1,C_VIN_2,C_VSYS1","11","100nF 16V X7R ±10% | CL05B104KO5NNNC | Samsung | 0402","Capacitor_SMD:C_0402_1005Metric","Samsung Electro-Mechanics","CL05B104KO5NNNC","C1525","","","",""
"R_BOOT_PU1,R_EN_PU1,R_STAT1,R_STAT2,R_TS1","5","10kΩ ±1% 62.5mW | 0402WGF1002TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF1002TCE","C25744","","","",""
"C_IMU_3","1","10nF 50V X7R ±10% | CL05B103KB5NNNC | Samsung | 0402","Capacitor_SMD:C_0402_1005Metric","Samsung Electro-Mechanics","CL05B103KB5NNNC","C15195","","","",""
@@ -16,11 +16,13 @@ Refs,Quantity,Value,Footprint,MF,MPN,LCSC,Mouser,DigiKey,Hand,DNP
"L_BUCK1","1","2.2µH ±20% 2.9A 44mΩ power inductor | SRN4018-2R2M | Bourns | SMD 4x4mm","Inductor_SMD:L_Bourns-SRN4018","Bourns","SRN4018-2R2M","C913207","","","",""
"R_VSYS1","1","200kΩ ±1% 62.5mW | 0402WGF2003TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF2003TCE","C25764","","","",""
"R_INV_BASE1,R_INV_PU1","2","220kΩ ±1% 62.5mW | 0402WGF2203TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF2203TCE","C25767","","","",""
+"R_PWR_EN_PD1","1","22kΩ ±1% 62.5mW | 0402WGF2202TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF2202TCE","C25768","","","",""
"C_BUCK_OUT1","1","22µF 25V X5R ±20% | CL21A226MAQNNNE | Samsung | 0805","Capacitor_SMD:C_0805_2012Metric","Samsung Electro-Mechanics","CL21A226MAQNNNE","C45783","","","",""
"R_FB1","1","255kΩ ±1% 62.5mW | RC0402FR-07255KL | Yageo | 0402","Resistor_SMD:R_0402_1005Metric","Yageo","RC0402FR-07255KL","C327361","","","",""
"R_USB_DM1,R_USB_DP1","2","27Ω ±1% 62.5mW | RC0402FR-0727RL | Yageo | 0402","Resistor_SMD:R_0402_1005Metric","Yageo","RC0402FR-0727RL","C138021","","","",""
"C_MCU_3","1","39pF 50V NP0 ±5% | CC0402JRNPO9BN390 | Yageo | 0402","Capacitor_SMD:C_0402_1005Metric","Yageo","CC0402JRNPO9BN390","C106223","","","",""
"R_I2C_SCL1,R_I2C_SDA1","2","4.7kΩ ±1% 62.5mW | 0402WGF4701TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF4701TCE","C25900","","","",""
+"C_LATCH_FB1","1","470nF 25V X7R ±10% | CL10B474KA8NNNC | Samsung | 0603","Capacitor_SMD:C_0603_1608Metric","Samsung Electro-Mechanics","CL10B474KA8NNNC","C1623","","","",""
"R_RGB1","1","470Ω ±1% 62.5mW | 0402WGF4700TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF4700TCE","C25117","","","",""
"R_CC1,R_CC2","2","5.1kΩ ±1% 62.5mW | 0402WGF5101TCE | UNI-ROYAL | 0402","Resistor_SMD:R_0402_1005Metric","UNI-ROYAL(Uniroyal Elec)","0402WGF5101TCE","C25905","","","",""
"R_FB2","1","56.2kΩ ±1% 62.5mW | RC0402FR-0756K2L | Yageo | 0402","Resistor_SMD:R_0402_1005Metric","Yageo","RC0402FR-0756K2L","C183355","","","",""
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
index 28ced3f..c38cda8 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Copper,L4,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
@@ -684,6 +684,14 @@ X127437500Y-65700000D03*
%TO.N,GND*%
X125562500Y-64750000D03*
%TD*%
+D36*
+%TO.P,C_LATCH_FB1,1*%
+%TO.N,/Power_Buck/PWR_EN*%
+X138175000Y-80800000D03*
+%TO.P,C_LATCH_FB1,2*%
+%TO.N,/Power_Control/PWR_LATCH_G*%
+X136625000Y-80800000D03*
+%TD*%
D45*
%TO.P,Q_INV1,1,B_1*%
%TO.N,/Power_Control/PWR_BTN_INV_BASE*%
@@ -798,10 +806,6 @@ X122700000Y-114100000D03*
X121100000Y-124880210D03*
%TO.N,/XBee/XBEE_SLEEP_RQ*%
X138900000Y-106200000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
%TO.N,/Buttons_Direct/BTN_MACRO5*%
X133300000Y-100800000D03*
X133100000Y-107000000D03*
@@ -848,6 +852,10 @@ X134700000Y-117700000D03*
X135600000Y-118300000D03*
%TO.N,/XBee/XBEE_RESET*%
X138200000Y-120550000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
%TO.N,VBUS*%
X124750000Y-95290000D03*
X122700000Y-102110000D03*
@@ -1309,27 +1317,6 @@ X139150000Y-105950000D02*
X139150000Y-103600000D01*
X138900000Y-106200000D02*
X139150000Y-105950000D01*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X142700000Y-97600000D02*
-X142700000Y-93500000D01*
-X143200000Y-98100000D02*
-X142700000Y-97600000D01*
-X142000000Y-107300000D02*
-X143200000Y-106100000D01*
-D48*
-X138385000Y-72440000D02*
-X138485000Y-72539999D01*
-D49*
-X143200000Y-106100000D02*
-X143200000Y-98100000D01*
-D48*
-X136935000Y-72440000D02*
-X138385000Y-72440000D01*
-D49*
-X140950000Y-91750000D02*
-X140950000Y-90700000D01*
-X142700000Y-93500000D02*
-X140950000Y-91750000D01*
%TO.N,/Buttons_Direct/BTN_MACRO5*%
X135460000Y-102100000D02*
X135460000Y-101840000D01*
@@ -1542,6 +1529,27 @@ X138200000Y-120550000D02*
X139150000Y-120550000D01*
X139150000Y-120550000D02*
X139150000Y-121300000D01*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X142700000Y-97600000D02*
+X142700000Y-93500000D01*
+X143200000Y-98100000D02*
+X142700000Y-97600000D01*
+X142000000Y-107300000D02*
+X143200000Y-106100000D01*
+D48*
+X138385000Y-72440000D02*
+X138485000Y-72539999D01*
+D49*
+X143200000Y-106100000D02*
+X143200000Y-98100000D01*
+D48*
+X136935000Y-72440000D02*
+X138385000Y-72440000D01*
+D49*
+X140950000Y-91750000D02*
+X140950000Y-90700000D01*
+X142700000Y-93500000D02*
+X140950000Y-91750000D01*
%TO.N,VBUS*%
D48*
X124750000Y-95290000D02*
@@ -1705,6 +1713,8 @@ X149108679Y-88500000D01*
D49*
X140425000Y-80240000D02*
X140425000Y-81010000D01*
+X138175000Y-80800000D02*
+X138280000Y-80800000D01*
D51*
X141643679Y-81035000D02*
X140400000Y-81035000D01*
@@ -1771,18 +1781,32 @@ X124861250Y-88965000D01*
X124861250Y-90539999D02*
X124661250Y-90740000D01*
%TO.N,/Power_Control/PWR_LATCH_G*%
+X133389999Y-77790000D02*
+X133384999Y-76940000D01*
X132334999Y-75440000D02*
X132334999Y-74900000D01*
X132334999Y-75440000D02*
X132785000Y-75440000D01*
+X135900000Y-80800000D02*
+X135050000Y-79950000D01*
X132334999Y-75889999D02*
X132334999Y-76490000D01*
X132334999Y-75889999D02*
X132334999Y-75440000D01*
X132334999Y-76490000D02*
X130134999Y-78690000D01*
+X135050000Y-79950000D02*
+X133850000Y-79950000D01*
X133634999Y-74590000D02*
X133634999Y-72440000D01*
+X133650000Y-79750000D02*
+X133650000Y-78050000D01*
+X133650000Y-78050000D02*
+X133389999Y-77790000D01*
+X133850000Y-79950000D02*
+X133650000Y-79750000D01*
+X136625000Y-80800000D02*
+X135900000Y-80800000D01*
X132785000Y-75440000D02*
X133634999Y-74590000D01*
X133935000Y-74889999D02*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
index 649bea5..8eb54ce 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Soldermask,Bot*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
@@ -3174,6 +3174,11 @@ X127437500Y-63800000D03*
X127437500Y-65700000D03*
X125562500Y-64750000D03*
%TD*%
+D40*
+%TO.C,C_LATCH_FB1*%
+X138175000Y-80800000D03*
+X136625000Y-80800000D03*
+%TD*%
D46*
%TO.C,Q_INV1*%
X124061300Y-86915000D03*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
index 0adf3f9..2a2a8f7 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Paste,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
@@ -540,6 +540,11 @@ X127437500Y-63800000D03*
X127437500Y-65700000D03*
X125562500Y-64750000D03*
%TD*%
+D29*
+%TO.C,C_LATCH_FB1*%
+X138175000Y-80800000D03*
+X136625000Y-80800000D03*
+%TD*%
D35*
%TO.C,Q_INV1*%
X124061300Y-86915000D03*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
index 1190789..16a1fcd 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Legend,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
@@ -3135,6 +3135,11 @@ X127560000Y-64700000D01*
X127800000Y-64370000D01*
X128040000Y-64700000D01*
G37*
+%TO.C,C_LATCH_FB1*%
+X137540580Y-80290000D02*
+X137259420Y-80290000D01*
+X137540580Y-81310000D02*
+X137259420Y-81310000D01*
%TO.C,Q_INV1*%
X124238800Y-84405000D02*
X124238800Y-84455000D01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr b/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
index 45aeb05..850be29 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
@@ -1,11 +1,11 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Profile,NP*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
index e865076..41ec00d 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Copper,L1,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
@@ -366,7 +366,7 @@ X139050000Y-105500000D03*
%TO.N,/Buttons_Direct/BTN_MACRO6*%
X138200000Y-105500000D03*
%TO.P,U_MCU1,7*%
-%TO.N,/MCU_Core/PWR_HOLD*%
+%TO.N,N/C*%
X137350000Y-105500000D03*
%TO.P,U_MCU1,8*%
%TO.N,/Buttons_Direct/BTN_MACRO3*%
@@ -461,12 +461,13 @@ X134800000Y-119500000D03*
%TO.N,/XBee/XBEE_ON_SLEEP*%
X135650000Y-119500000D03*
%TO.P,U_MCU1,38*%
-%TO.N,N/C*%
+%TO.N,/XBee/XBEE_RESET*%
X136500000Y-119500000D03*
%TO.P,U_MCU1,39*%
+%TO.N,N/C*%
X137350000Y-119500000D03*
%TO.P,U_MCU1,40*%
-%TO.N,/XBee/XBEE_RESET*%
+%TO.N,/MCU_Core/PWR_HOLD*%
X138200000Y-119500000D03*
%TO.P,U_MCU1,41*%
%TO.N,N/C*%
@@ -901,10 +902,6 @@ X122700000Y-114100000D03*
X121100000Y-124880210D03*
%TO.N,/XBee/XBEE_SLEEP_RQ*%
X138900000Y-106200000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
%TO.N,/Buttons_Direct/BTN_MACRO5*%
X133300000Y-100800000D03*
X133100000Y-107000000D03*
@@ -951,6 +948,10 @@ X134700000Y-117700000D03*
X135600000Y-118300000D03*
%TO.N,/XBee/XBEE_RESET*%
X138200000Y-120550000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
%TO.N,VBUS*%
X124750000Y-95290000D03*
X122700000Y-102110000D03*
@@ -1563,27 +1564,6 @@ X139050000Y-106050000D02*
X138900000Y-106200000D01*
X139050000Y-105500000D02*
X139050000Y-106050000D01*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X138485000Y-74588529D02*
-X138485000Y-72539999D01*
-X136825000Y-76248529D02*
-X138485000Y-74588529D01*
-X137650000Y-106400000D02*
-X138650000Y-107400000D01*
-X137650000Y-105800000D02*
-X137650000Y-106400000D01*
-X136825000Y-84840255D02*
-X136825000Y-76248529D01*
-X137350000Y-105500000D02*
-X137650000Y-105800000D01*
-X141900000Y-107400000D02*
-X142000000Y-107300000D01*
-X140950000Y-88965255D02*
-X136825000Y-84840255D01*
-X140950000Y-90700000D02*
-X140950000Y-88965255D01*
-X138650000Y-107400000D02*
-X141900000Y-107400000D01*
%TO.N,/MCU_Core/STICK_Y*%
X131400000Y-93051471D02*
X133948529Y-93051471D01*
@@ -1917,8 +1897,37 @@ X135600000Y-118300000D01*
X135650000Y-119500000D02*
X135650000Y-118350000D01*
%TO.N,/XBee/XBEE_RESET*%
-X138200000Y-119500000D02*
+X137050000Y-120550000D02*
X138200000Y-120550000D01*
+X136500000Y-120000000D02*
+X137050000Y-120550000D01*
+X136500000Y-119500000D02*
+X136500000Y-120000000D01*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X138485000Y-74588529D02*
+X138485000Y-72539999D01*
+X141400000Y-113951471D02*
+X141751471Y-113600000D01*
+X136825000Y-76248529D02*
+X138485000Y-74588529D01*
+X138450000Y-118750000D02*
+X141400000Y-115800000D01*
+X136825000Y-84840255D02*
+X136825000Y-76248529D01*
+X140950000Y-88965255D02*
+X136825000Y-84840255D01*
+X140950000Y-90700000D02*
+X140950000Y-88965255D01*
+X142000000Y-113600000D02*
+X142000000Y-107300000D01*
+X141400000Y-115800000D02*
+X141400000Y-113951471D01*
+X138200000Y-119500000D02*
+X138200000Y-119000000D01*
+X141751471Y-113600000D02*
+X142000000Y-113600000D01*
+X138200000Y-119000000D02*
+X138450000Y-118750000D01*
%TO.N,VBUS*%
D53*
X137000000Y-124900000D02*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
index a1cb87f..e49bb7f 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Soldermask,Top*%
%TF.FilePolarity,Negative*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
index 97eefb5..ffdd2b1 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Paste,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
index 004d62f..7f9b1bf 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Legend,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
index d3eb398..dfee322 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Copper,L2,Inr*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
@@ -197,10 +197,6 @@ X122700000Y-114100000D03*
X121100000Y-124880210D03*
%TO.N,/XBee/XBEE_SLEEP_RQ*%
X138900000Y-106200000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
%TO.N,/Buttons_Direct/BTN_MACRO5*%
X133300000Y-100800000D03*
X133100000Y-107000000D03*
@@ -247,6 +243,10 @@ X134700000Y-117700000D03*
X135600000Y-118300000D03*
%TO.N,/XBee/XBEE_RESET*%
X138200000Y-120550000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
%TO.N,VBUS*%
X124750000Y-95290000D03*
X122700000Y-102110000D03*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
index eb8a509..b82f2c1 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:07:59-08:00*%
+%TF.CreationDate,2026-11-01T11:55:16-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Copper,L3,Inr*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:16*
%MOMM*%
%LPD*%
G01*
@@ -197,10 +197,6 @@ X122700000Y-114100000D03*
X121100000Y-124880210D03*
%TO.N,/XBee/XBEE_SLEEP_RQ*%
X138900000Y-106200000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
%TO.N,/Buttons_Direct/BTN_MACRO5*%
X133300000Y-100800000D03*
X133100000Y-107000000D03*
@@ -247,6 +243,10 @@ X134700000Y-117700000D03*
X135600000Y-118300000D03*
%TO.N,/XBee/XBEE_RESET*%
X138200000Y-120550000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
%TO.N,VBUS*%
X124750000Y-95290000D03*
X122700000Y-102110000D03*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl b/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
index 2a7e9f0..7ed3fcb 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
+++ b/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
@@ -1,7 +1,7 @@
M48
-; DRILL file KiCad 10.0.5 date 2026-11-01T11:07:59
+; DRILL file KiCad 10.0.5 date 2026-11-01T11:55:16
; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-11-01T11:07:59-08:00
+; #@! TF.CreationDate,2026-11-01T11:55:16-08:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
; #@! TF.FileFunction,NonPlated,1,4,NPTH
FMAT,2
diff --git a/PCB/v2.x/production/gerbers/snips_controller-PTH.drl b/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
index 9d4c954..4766430 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
+++ b/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
@@ -1,7 +1,7 @@
M48
-; DRILL file KiCad 10.0.5 date 2026-11-01T11:07:59
+; DRILL file KiCad 10.0.5 date 2026-11-01T11:55:16
; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-11-01T11:07:59-08:00
+; #@! TF.CreationDate,2026-11-01T11:55:16-08:00
; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
; #@! TF.FileFunction,Plated,1,4,PTH
FMAT,2
diff --git a/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob b/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
index d796eec..486f80a 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
+++ b/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
@@ -5,7 +5,7 @@
"Application": "Pcbnew",
"Version": "10.0.5"
},
- "CreationDate": "2026-11-01T11:07:59-08:00"
+ "CreationDate": "2026-11-01T11:55:16-08:00"
},
"GeneralSpecs": {
"ProjectId": {
diff --git a/PCB/v2.x/production/gerbers/snips_controller.zip b/PCB/v2.x/production/gerbers/snips_controller.zip
index fc8e74f..0819e6c 100644
Binary files a/PCB/v2.x/production/gerbers/snips_controller.zip and b/PCB/v2.x/production/gerbers/snips_controller.zip differ
diff --git a/PCB/v2.x/production/jlcpcb/Snips_2_0.zip b/PCB/v2.x/production/jlcpcb/Snips_2_0.zip
index d16b27c..c9a92bc 100644
Binary files a/PCB/v2.x/production/jlcpcb/Snips_2_0.zip and b/PCB/v2.x/production/jlcpcb/Snips_2_0.zip differ
diff --git a/PCB/v2.x/production/jlcpcb/netlist.ipc b/PCB/v2.x/production/jlcpcb/netlist.ipc
index 5049bc2..b4fedc1 100644
--- a/PCB/v2.x/production/jlcpcb/netlist.ipc
+++ b/PCB/v2.x/production/jlcpcb/netlist.ipc
@@ -77,9 +77,6 @@ P arrayDim N
317OMETER/I2C_SCL VIA MD0118PA00X+048307Y-044921X0236Y0000R000S3
317OMETER/I2C_SCL VIA MD0118PA00X+047677Y-049165X0236Y0000R000S3
317/XBEE_SLEEP_RQ VIA MD0118PA00X+054685Y-041811X0236Y0000R000S3
-317_CORE/PWR_HOLD VIA MD0118PA00X+055492Y-035709X0236Y0000R000S3
-317_CORE/PWR_HOLD VIA MD0118PA00X+054522Y-028559X0236Y0000R000S3
-317_CORE/PWR_HOLD VIA MD0118PA00X+055906Y-042244X0236Y0000R000S3
317ECT/BTN_MACRO5 VIA MD0118PA00X+052480Y-039685X0236Y0000R000S3
317ECT/BTN_MACRO5 VIA MD0118PA00X+052402Y-042126X0236Y0000R000S3
317ECT/BTN_MACRO5 VIA MD0118PA00X+053607Y-039818X0236Y0000R000S3
@@ -110,6 +107,9 @@ P arrayDim N
317ECT/BTN_VOL_DN VIA MD0118PA00X+053031Y-046339X0236Y0000R000S3
317/XBEE_ON_SLEEP VIA MD0118PA00X+053386Y-046575X0236Y0000R000S3
317BEE/XBEE_RESET VIA MD0118PA00X+054409Y-047461X0236Y0000R000S3
+317_CORE/PWR_HOLD VIA MD0118PA00X+055492Y-035709X0236Y0000R000S3
+317_CORE/PWR_HOLD VIA MD0118PA00X+054522Y-028559X0236Y0000R000S3
+317_CORE/PWR_HOLD VIA MD0118PA00X+055906Y-042244X0236Y0000R000S3
317VBUS VIA MD0118PA00X+049114Y-037516X0236Y0000R000S3
317VBUS VIA MD0118PA00X+048307Y-040201X0236Y0000R000S3
317VBUS VIA MD0118PA00X+053937Y-049173X0236Y0000R000S3
@@ -195,7 +195,7 @@ P arrayDim N
327_CORE/MCU_BOOT U_MCU1-4 A01X+055079Y-041535X0157Y0315R000S2
327/XBEE_SLEEP_RQ U_MCU1-5 A01X+054744Y-041535X0157Y0315R000S2
327ECT/BTN_MACRO6 U_MCU1-6 A01X+054409Y-041535X0157Y0315R000S2
-327_CORE/PWR_HOLD U_MCU1-7 A01X+054075Y-041535X0157Y0315R000S2
+327N/C U_MCU1-7 A01X+054075Y-041535X0157Y0315R000S2
327ECT/BTN_MACRO3 U_MCU1-8 A01X+053740Y-041535X0157Y0315R000S2
327ECT/BTN_MACRO2 U_MCU1-9 A01X+053406Y-041535X0157Y0315R000S2
327U_CORE/STICK_Y U_MCU1-10 A01X+053071Y-041535X0157Y0315R000S2
@@ -226,9 +226,9 @@ P arrayDim N
327/XBEE/XBEE_RTS U_MCU1-35 A01X+052736Y-047047X0157Y0315R000S2
327ECT/BTN_VOL_DN U_MCU1-36 A01X+053071Y-047047X0157Y0315R000S2
327/XBEE_ON_SLEEP U_MCU1-37 A01X+053406Y-047047X0157Y0315R000S2
-327N/C U_MCU1-38 A01X+053740Y-047047X0157Y0315R000S2
+327BEE/XBEE_RESET U_MCU1-38 A01X+053740Y-047047X0157Y0315R000S2
327N/C U_MCU1-39 A01X+054075Y-047047X0157Y0315R000S2
-327BEE/XBEE_RESET U_MCU1-40 A01X+054409Y-047047X0157Y0315R000S2
+327_CORE/PWR_HOLD U_MCU1-40 A01X+054409Y-047047X0157Y0315R000S2
327N/C U_MCU1-41 A01X+054744Y-047047X0157Y0315R000S2
327GND U_MCU1-42 A01X+055079Y-047047X0157Y0315R000S2
327GND U_MCU1-43 A01X+055413Y-047047X0157Y0315R000S2
@@ -485,6 +485,8 @@ P arrayDim N
3273V3 U_HALL-1 A04X+050172Y-025118X0581Y0236R180S1
327ER/TRIG_ANALOG U_HALL-2 A04X+050172Y-025866X0581Y0236R180S1
327GND U_HALL-3 A04X+049434Y-025492X0581Y0236R180S1
+327ER_BUCK/PWR_EN C_LATC-1 A04X+054400Y-031811X0354Y0374R180S1
+327OL/PWR_LATCH_G C_LATC-2 A04X+053789Y-031811X0354Y0374R180S1
327R_BTN_INV_BASE Q_INV1-1 A04X+048843Y-034219X0581Y0236R000S1
327GND Q_INV1-2 A04X+048843Y-033470X0581Y0236R000S1
327WR_BTN_TRIGGER Q_INV1-3 A04X+049581Y-033844X0581Y0236R000S1
diff --git a/PCB/v2.x/production/placement/snips_controller-all.pos b/PCB/v2.x/production/placement/snips_controller-all.pos
index daf9f1b..31682f8 100644
--- a/PCB/v2.x/production/placement/snips_controller-all.pos
+++ b/PCB/v2.x/production/placement/snips_controller-all.pos
@@ -1,4 +1,4 @@
-### Footprint positions - created on 2026-11-01T11:07:59 ###
+### Footprint positions - created on 2026-11-01T11:55:16 ###
### Printed by KiCad version 10.0.5
## Unit = mm, Angle = deg.
## Side : All
@@ -11,6 +11,7 @@ C_HALL1 100nF_16V_X7R_±10%_|_CL05B104KO5NNNC_|_Samsung_|_0402
C_IMU_1 100nF_16V_X7R_±10%_|_CL05B104KO5NNNC_|_Samsung_|_0402 C_0402_1005Metric 127.2000 -125.9000 0.0000 bottom
C_IMU_2 2.2µF_10V_X7R_±10%_|_CL10B225KP8NNNC_|_Samsung_|_0603 C_0603_1608Metric 124.7000 -125.7000 180.0000 bottom
C_IMU_3 10nF_50V_X7R_±10%_|_CL05B103KB5NNNC_|_Samsung_|_0402 C_0402_1005Metric 127.1800 -128.5000 180.0000 bottom
+C_LATCH_FB1 470nF_25V_X7R_±10%_|_CL10B474KA8NNNC_|_Samsung_|_0603 C_0603_1608Metric 137.4000 -80.8000 180.0000 bottom
C_LATCH_G1 1µF_6.3V_X5R_±10%_|_CL05A105KQ5NNNC_|_Samsung_|_0402 C_0402_1005Metric 135.0050 -74.8900 180.0000 bottom
C_STICK1 100nF_16V_X7R_±10%_|_CL05B104KO5NNNC_|_Samsung_|_0402 C_0402_1005Metric 145.5050 -76.2050 -90.0000 bottom
C_SYS_1 10µF_25V_X5R_±10%_|_CL21A106KAYNNNE_|_Samsung_|_0805 C_0805_2012Metric 134.7000 -94.2500 0.0000 bottom
@@ -38,7 +39,7 @@ R_INV_BASE1 220kΩ_±1%_62.5mW_|_0402WGF2203TCE_|_UNI-ROYAL_|_0402
R_INV_PU1 220kΩ_±1%_62.5mW_|_0402WGF2203TCE_|_UNI-ROYAL_|_0402 R_0402_1005Metric 128.4613 -91.2150 90.0000 bottom
R_ISET1 604Ω_±1%_62.5mW_|_AC0402FR-07604RL_|_Yageo_|_0402 R_0402_1005Metric 121.7900 -98.2500 180.0000 bottom
R_LATCH_G1 1MΩ_±1%_62.5mW_|_0402WGF1004TCE_|_UNI-ROYAL_|_0402 R_0402_1005Metric 132.2850 -74.4400 0.0000 bottom
-R_PWR_EN_PD1 100kΩ_±1%_62.5mW_|_0402WGF1003TCE_|_UNI-ROYAL_|_0402 R_0402_1005Metric 140.9350 -80.2400 0.0000 bottom
+R_PWR_EN_PD1 22kΩ_±1%_62.5mW_|_0402WGF2202TCE_|_UNI-ROYAL_|_0402 R_0402_1005Metric 140.9350 -80.2400 0.0000 bottom
R_STAT1 10kΩ_±1%_62.5mW_|_0402WGF1002TCE_|_UNI-ROYAL_|_0402 R_0402_1005Metric 124.1600 -97.2500 180.0000 bottom
R_STAT2 10kΩ_±1%_62.5mW_|_0402WGF1002TCE_|_UNI-ROYAL_|_0402 R_0402_1005Metric 133.3500 -100.0500 0.0000 bottom
R_TRIG1 1kΩ_±1%_62.5mW_|_0402WGF1001TCE_|_UNI-ROYAL_|_0402 R_0402_1005Metric 129.7500 -91.2500 -90.0000 bottom
diff --git a/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr b/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
index 1c9ee0c..afe1842 100644
--- a/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
+++ b/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:08:00-08:00*%
+%TF.CreationDate,2026-11-01T11:55:17-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Component,L4,Bot*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:08:00*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:17*
%MOMM*%
%LPD*%
G01*
@@ -304,7 +304,7 @@ X126835000Y-78690000D03*
D10*
%TO.C,R_PWR_EN_PD1*%
%TO.CFtp,R_0402_1005Metric*%
-%TO.CVal,100kΩ ±1\u0025 62.5mW | 0402WGF1003TCE | UNI-ROYAL | 0402*%
+%TO.CVal,22kΩ ±1\u0025 62.5mW | 0402WGF2202TCE | UNI-ROYAL | 0402*%
%TO.CLbN,Resistor_SMD*%
%TO.CMnt,SMD*%
%TO.CRot,180*%
@@ -1044,6 +1044,26 @@ X127437500Y-65700000D03*
X125562500Y-64750000D03*
%TD*%
D10*
+%TO.C,C_LATCH_FB1*%
+%TO.CFtp,C_0603_1608Metric*%
+%TO.CVal,470nF 25V X7R ±10\u0025 | CL10B474KA8NNNC | Samsung | 0603*%
+%TO.CMnt,SMD*%
+%TO.CRot,0*%
+X137400000Y-80800000D03*
+D11*
+X138875000Y-80075000D02*
+X138875000Y-81525000D01*
+X135925000Y-81525000D01*
+X135925000Y-80075000D01*
+X138875000Y-80075000D01*
+D12*
+%TO.P,C_LATCH_FB1,1*%
+X138175000Y-80800000D03*
+D13*
+%TO.P,C_LATCH_FB1,2*%
+X136625000Y-80800000D03*
+%TD*%
+D10*
%TO.C,Q_INV1*%
%TO.CFtp,SOT-23*%
%TO.CVal,NPN transistor 40V 200mA hFE 100-300 | MMBT3904(RANGE:100-300) | JCET | SOT-23*%
diff --git a/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr b/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
index b820cc1..8e49eb7 100644
--- a/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
+++ b/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
@@ -1,12 +1,12 @@
%TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T11:08:00-08:00*%
+%TF.CreationDate,2026-11-01T11:55:17-08:00*%
%TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
%TF.SameCoordinates,Original*%
%TF.FileFunction,Component,L1,Top*%
%TF.FilePolarity,Positive*%
%FSLAX46Y46*%
G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:08:00*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:55:17*
%MOMM*%
%LPD*%
G01*
diff --git a/PCB/v2.x/snips_controller.kicad_pcb b/PCB/v2.x/snips_controller.kicad_pcb
index 9744236..7fc390e 100644
--- a/PCB/v2.x/snips_controller.kicad_pcb
+++ b/PCB/v2.x/snips_controller.kicad_pcb
@@ -257,7 +257,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:82"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:86"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -1502,7 +1502,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:78"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:82"
(at -2 0 0)
(layer "F.SilkS")
(hide yes)
@@ -1882,7 +1882,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:108"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:112"
(at 0 2 90)
(layer "F.SilkS")
(hide yes)
@@ -2158,7 +2158,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:80"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:84"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -2758,7 +2758,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:73"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:77"
(at 0 2 90)
(layer "F.SilkS")
(hide yes)
@@ -2961,7 +2961,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:87"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:91"
(at 2 0 0)
(layer "F.SilkS")
(hide yes)
@@ -3407,7 +3407,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:84"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:88"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -3779,7 +3779,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:81"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:85"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -4151,7 +4151,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:79"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:83"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -4852,7 +4852,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:111"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:115"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -5725,7 +5725,7 @@
(justify mirror)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:100"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:104"
(at 0 -2 90)
(layer "F.SilkS")
(hide yes)
@@ -5988,7 +5988,6 @@
(at -7 -0.85)
(size 0.4 0.8)
(layers "F.Cu" "F.Mask" "F.Paste")
- (net "/MCU_Core/PWR_HOLD")
(uuid "875768b4-6053-4494-8588-1ade1ee79bbe")
)
(pad "8" smd rect
@@ -6204,6 +6203,7 @@
(at 7 0)
(size 0.4 0.8)
(layers "F.Cu" "F.Mask" "F.Paste")
+ (net "/XBee/XBEE_RESET")
(uuid "058f594b-a9c1-4900-8375-c0b6f857f603")
)
(pad "39" smd rect
@@ -6216,7 +6216,7 @@
(at 7 -1.7)
(size 0.4 0.8)
(layers "F.Cu" "F.Mask" "F.Paste")
- (net "/XBee/XBEE_RESET")
+ (net "/MCU_Core/PWR_HOLD")
(uuid "44c91ce2-6d63-421d-a44d-b3e40a2f1405")
)
(pad "41" smd rect
@@ -6589,7 +6589,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:89"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:93"
(at -2 0 0)
(layer "F.SilkS")
(hide yes)
@@ -8291,7 +8291,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:69"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:73"
(at -2 0 0)
(layer "F.SilkS")
(hide yes)
@@ -8607,7 +8607,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:76"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:80"
(at 0 2 90)
(layer "F.SilkS")
(hide yes)
@@ -8824,7 +8824,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:105"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:109"
(at 0 2 90)
(layer "F.SilkS")
(hide yes)
@@ -9027,7 +9027,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:86"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:90"
(at 2 0 0)
(layer "F.SilkS")
(hide yes)
@@ -9920,7 +9920,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:104"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:108"
(at 0 2 90)
(layer "F.SilkS")
(hide yes)
@@ -10123,7 +10123,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:90"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:94"
(at -2 0 0)
(layer "F.SilkS")
(hide yes)
@@ -10633,7 +10633,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:77"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:81"
(at 0 -2 0)
(layer "F.SilkS")
(hide yes)
@@ -10845,7 +10845,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:85"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:89"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -11406,7 +11406,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:74"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:78"
(at 0 2 90)
(layer "F.SilkS")
(hide yes)
@@ -11606,7 +11606,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:83"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:87"
(at 0 2 0)
(layer "F.SilkS")
(hide yes)
@@ -15463,7 +15463,7 @@
(justify mirror)
)
)
- (property "Value" "100kΩ ±1% 62.5mW | 0402WGF1003TCE | UNI-ROYAL | 0402"
+ (property "Value" "22kΩ ±1% 62.5mW | 0402WGF2202TCE | UNI-ROYAL | 0402"
(at 0 -1.17 0)
(layer "B.Fab")
(uuid "190badc0-99f5-49cd-a801-6ac92a88ce63")
@@ -15526,7 +15526,7 @@
(justify mirror)
)
)
- (property "Manufacturer_Part_Number" "0402WGF1003TCE"
+ (property "Manufacturer_Part_Number" "0402WGF2202TCE"
(at 0 0 180)
(unlocked yes)
(layer "B.Fab")
@@ -15540,7 +15540,7 @@
(justify mirror)
)
)
- (property "LCSC" "C25741"
+ (property "LCSC" "C25768"
(at 0 0 180)
(unlocked yes)
(layer "B.Fab")
@@ -18497,7 +18497,7 @@
(justify mirror)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:110"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:114"
(at 0 -2 90)
(layer "B.SilkS")
(hide yes)
@@ -19583,7 +19583,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:64"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:68"
(at 0 -2 0)
(layer "B.SilkS")
(hide yes)
@@ -19804,7 +19804,7 @@
(justify mirror)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:88"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:92"
(at 0 2 0)
(layer "B.SilkS")
(hide yes)
@@ -20271,7 +20271,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:65"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:69"
(at -2 0 0)
(layer "B.SilkS")
(hide yes)
@@ -22182,7 +22182,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:92"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:96"
(at 0 -2 180)
(layer "B.SilkS")
(hide yes)
@@ -22985,7 +22985,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:71"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:75"
(at 0 2 180)
(layer "B.SilkS")
(hide yes)
@@ -24055,7 +24055,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:67"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:71"
(at -2 0 270)
(layer "B.SilkS")
(hide yes)
@@ -24487,7 +24487,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:75"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:79"
(at 0 -2 180)
(layer "B.SilkS")
(hide yes)
@@ -24934,7 +24934,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:70"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:74"
(at 0 -2 180)
(layer "B.SilkS")
(hide yes)
@@ -25150,7 +25150,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:66"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:70"
(at 0 -2 180)
(layer "B.SilkS")
(hide yes)
@@ -25785,7 +25785,7 @@
(justify mirror)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:103"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:107"
(at 0 -2 180)
(layer "B.SilkS")
(hide yes)
@@ -26206,7 +26206,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:91"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:95"
(at -2 0 180)
(layer "B.SilkS")
(hide yes)
@@ -27472,7 +27472,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:109"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:113"
(at 0 -2 180)
(layer "B.SilkS")
(hide yes)
@@ -27790,6 +27790,238 @@
)
)
)
+ (footprint "C_0603_1608Metric"
+ (layer "B.Cu")
+ (uuid "f181f9ee-f3d1-47cd-a7ea-005b1d09ceb6")
+ (at 137.4 80.8 180)
+ (descr "Capacitor SMD 0603 (1608 Metric), square (rectangular) end terminal, IPC-7351 nominal, (Body size source: IPC-SM-782 page 76, https://www.pcb-3d.com/wordpress/wp-content/uploads/ipc-sm-782a_amendment_1_and_2.pdf)")
+ (tags "capacitor")
+ (property "Reference" "C_LATCH_FB1"
+ (at 0 1.43 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "0ba5b52f-2293-483c-8458-2ebf8e0e9d90")
+ (effects
+ (font
+ (size 1 1)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "Value" "470nF 25V X7R ±10% | CL10B474KA8NNNC | Samsung | 0603"
+ (at 0 -1.43 0)
+ (layer "B.Fab")
+ (uuid "36557735-6d4f-49c3-8576-f9ec90382a28")
+ (effects
+ (font
+ (size 1 1)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "Datasheet" ""
+ (at 0 0 0)
+ (layer "B.Fab")
+ (hide yes)
+ (uuid "b4366711-c40f-4deb-b7ea-c286ab5a4238")
+ (effects
+ (font
+ (size 1.27 1.27)
+ )
+ (justify mirror)
+ )
+ )
+ (property "Description" ""
+ (at 0 0 0)
+ (layer "B.Fab")
+ (hide yes)
+ (uuid "49aa5089-3329-4e0f-abfc-ee3fccc9e7b8")
+ (effects
+ (font
+ (size 1.27 1.27)
+ )
+ (justify mirror)
+ )
+ )
+ (property "KiLib_Generator" "SMD_2terminal_chip_molded"
+ (at 0 0 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "ec1593d0-b1dd-472f-beae-a94977a3a847")
+ (effects
+ (font
+ (size 1 1)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "Voltage" "25V"
+ (at 0 -2 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "7c9b5b0e-b0d1-4397-a4ea-2fd52fdeb6b6")
+ (effects
+ (font
+ (size 1.27 1.27)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "MF" "Samsung Electro-Mechanics"
+ (at 0 -2 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "3f041233-72d5-4316-a210-ee23e893717c")
+ (effects
+ (font
+ (size 1.27 1.27)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "Manufacturer_Part_Number" "CL10B474KA8NNNC"
+ (at 0 -2 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "f61328c6-eb87-4db3-88ed-e9a09de0f261")
+ (effects
+ (font
+ (size 1.27 1.27)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "LCSC" "C1623"
+ (at 0 -2 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "945491cd-b6f6-41f8-8019-62db5c200e32")
+ (effects
+ (font
+ (size 1.27 1.27)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "Stackup Path" "C_LATCH_FB1"
+ (at 0 -2 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "18e211c0-3a4a-4045-8f93-50ee16d1eb48")
+ (effects
+ (font
+ (size 1.27 1.27)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:67"
+ (at 0 -2 0)
+ (layer "B.SilkS")
+ (hide yes)
+ (uuid "8e218344-840c-4edd-91d4-a19fe90d8248")
+ (effects
+ (font
+ (size 1.27 1.27)
+ (thickness 0.15)
+ )
+ (justify mirror)
+ )
+ )
+ (path "/206b3358-4a33-5087-8c48-0c601a1b3b90")
+ (attr smd)
+ (duplicate_pad_numbers_are_jumpers no)
+ (fp_line
+ (start -0.14058 0.51)
+ (end 0.14058 0.51)
+ (stroke
+ (width 0.12)
+ (type solid)
+ )
+ (layer "B.SilkS")
+ (uuid "6fe503ab-54f8-43f9-a9f2-777bd3e1a671")
+ )
+ (fp_line
+ (start -0.14058 -0.51)
+ (end 0.14058 -0.51)
+ (stroke
+ (width 0.12)
+ (type solid)
+ )
+ (layer "B.SilkS")
+ (uuid "774f7fc0-83bb-4d33-b806-f45cb06073ac")
+ )
+ (fp_rect
+ (start -1.48 0.73)
+ (end 1.48 -0.73)
+ (stroke
+ (width 0.05)
+ (type solid)
+ )
+ (fill no)
+ (layer "B.CrtYd")
+ (uuid "cafcaf73-7db5-4b66-9a71-2f4fc3f1557e")
+ )
+ (fp_rect
+ (start -0.8 0.4)
+ (end 0.8 -0.4)
+ (stroke
+ (width 0.1)
+ (type solid)
+ )
+ (fill no)
+ (layer "B.Fab")
+ (uuid "43caa6a5-aeec-485f-b1b5-fba5b250791a")
+ )
+ (fp_text user "${REFERENCE}"
+ (at 0 0 0)
+ (layer "B.Fab")
+ (uuid "b9c4bbc5-b5ef-4671-af38-31f7ad5b46d8")
+ (effects
+ (font
+ (size 0.4 0.4)
+ (thickness 0.06)
+ )
+ (justify mirror)
+ )
+ )
+ (pad "1" smd roundrect
+ (at -0.775 0 180)
+ (size 0.9 0.95)
+ (layers "B.Cu" "B.Mask" "B.Paste")
+ (roundrect_rratio 0.25)
+ (net "/Power_Buck/PWR_EN")
+ (uuid "7d52daa2-9374-4904-bb5f-ced7aa057bfa")
+ )
+ (pad "2" smd roundrect
+ (at 0.775 0 180)
+ (size 0.9 0.95)
+ (layers "B.Cu" "B.Mask" "B.Paste")
+ (roundrect_rratio 0.25)
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "16fd4623-3c18-4057-9795-254b5ab2b53f")
+ )
+ (embedded_fonts no)
+ (model "${KICAD10_3DMODEL_DIR}/Capacitor_SMD.3dshapes/C_0603_1608Metric.step"
+ (offset
+ (xyz 0 0 0)
+ )
+ (scale
+ (xyz 1 1 1)
+ )
+ (rotate
+ (xyz 0 0 0)
+ )
+ )
+ )
(footprint "Package_TO_SOT_SMD:SOT-23"
(layer "B.Cu")
(uuid "f2c12f4d-8edf-48f9-b147-c8a6b7a99159")
@@ -28390,7 +28622,7 @@
(justify mirror)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:107"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:111"
(at 0 -2 270)
(layer "B.SilkS")
(hide yes)
@@ -28598,7 +28830,7 @@
)
)
)
- (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:72"
+ (property "Stackup Source" "PCB/v2.x/stackup/board.kdl:76"
(at 0 -2 180)
(layer "B.SilkS")
(hide yes)
@@ -33086,174 +33318,6 @@
(net "/XBee/XBEE_SLEEP_RQ")
(uuid "7e57f38d-a598-416e-86e2-ec7774bbd1f0")
)
- (segment
- (start 138.485 74.588529)
- (end 138.485 72.539999)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "1db3e63b-d7d3-4271-a9fa-b0796ffa017e")
- )
- (segment
- (start 136.825 76.248529)
- (end 138.485 74.588529)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "348f6de3-76c0-42e3-a994-073f34529097")
- )
- (segment
- (start 137.65 106.4)
- (end 138.65 107.4)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "46b8ffd9-ea1b-41dc-9cd4-f618d095da8f")
- )
- (segment
- (start 137.65 105.8)
- (end 137.65 106.4)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "604c8aa3-6520-4ac3-99f9-31d1fb6e943e")
- )
- (segment
- (start 136.825 84.840255)
- (end 136.825 76.248529)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "61817c01-9c98-4fda-b123-3f35bcab8fc6")
- )
- (segment
- (start 137.35 105.5)
- (end 137.65 105.8)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "65e3233a-b642-460e-a68a-0061e04dbd21")
- )
- (segment
- (start 141.9 107.4)
- (end 142 107.3)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "7083ba98-6af6-49fa-9d9b-e8e586e70a4f")
- )
- (segment
- (start 140.95 88.965255)
- (end 136.825 84.840255)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "72b4cbb2-270b-4dba-a8f2-9035c9be5946")
- )
- (segment
- (start 140.95 90.7)
- (end 140.95 88.965255)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "744df1f1-4804-400b-b298-cc600628305f")
- )
- (segment
- (start 138.65 107.4)
- (end 141.9 107.4)
- (width 0.2)
- (layer "F.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "864f962f-a328-4888-a021-4b04abbe7d55")
- )
- (via
- (at 140.95 90.7)
- (size 0.6)
- (drill 0.3)
- (layers "F.Cu" "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "01e75d0e-132e-4c32-a7ed-7e79123a0c57")
- )
- (via
- (at 138.485 72.539999)
- (size 0.6)
- (drill 0.3)
- (layers "F.Cu" "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "034ec525-4d56-4b3b-91b8-82fff126752d")
- )
- (via
- (at 142 107.3)
- (size 0.6)
- (drill 0.3)
- (layers "F.Cu" "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "54dfdcc4-7e5a-46db-a25d-9b3f49cfd01b")
- )
- (segment
- (start 142.7 97.6)
- (end 142.7 93.5)
- (width 0.2)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "09fe6f92-9e04-4ba4-9d03-c073381dc901")
- )
- (segment
- (start 143.2 98.1)
- (end 142.7 97.6)
- (width 0.2)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "3f31b1e1-abb7-4e71-b528-b60fbe25a48b")
- )
- (segment
- (start 142 107.3)
- (end 143.2 106.1)
- (width 0.2)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "41733a2e-2396-4c5b-9393-66bf3739c162")
- )
- (segment
- (start 138.385 72.44)
- (end 138.485 72.539999)
- (width 0.3)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "59dd0f51-8058-4c5b-bda6-638a82a844c7")
- )
- (segment
- (start 143.2 106.1)
- (end 143.2 98.1)
- (width 0.2)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "6b699eb9-7b8d-4f12-abba-c838def9d377")
- )
- (segment
- (start 136.935 72.44)
- (end 138.385 72.44)
- (width 0.3)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "89103954-78e1-436f-92b5-11159941f3b9")
- )
- (segment
- (start 140.95 91.75)
- (end 140.95 90.7)
- (width 0.2)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "b6b0213f-7930-422d-abcf-9df4dbf4a136")
- )
- (segment
- (start 142.7 93.5)
- (end 140.95 91.75)
- (width 0.2)
- (layer "B.Cu")
- (net "/MCU_Core/PWR_HOLD")
- (uuid "c221372f-870c-4836-90f0-577b1e33d84b")
- )
(segment
(start 131.4 93.051471)
(end 133.948529 93.051471)
@@ -35503,12 +35567,28 @@
(uuid "d7d1562f-bb55-429b-b8ed-46044ca26d28")
)
(segment
- (start 138.2 119.5)
+ (start 137.05 120.55)
(end 138.2 120.55)
(width 0.2)
(layer "F.Cu")
(net "/XBee/XBEE_RESET")
- (uuid "2e0f3a48-2760-4244-b9d2-b93633a2633d")
+ (uuid "22a6e6b8-cb52-4796-a547-05f25a6b7011")
+ )
+ (segment
+ (start 136.5 120)
+ (end 137.05 120.55)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/XBee/XBEE_RESET")
+ (uuid "535a689a-3fa5-4f74-9150-51e5b2b9b778")
+ )
+ (segment
+ (start 136.5 119.5)
+ (end 136.5 120)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/XBee/XBEE_RESET")
+ (uuid "60ef5843-84db-4a65-ae0a-1aada411f14d")
)
(via
(at 138.2 120.55)
@@ -35534,6 +35614,190 @@
(net "/XBee/XBEE_RESET")
(uuid "a4abc012-ddf7-4806-a578-8f1f76ef20d1")
)
+ (segment
+ (start 138.485 74.588529)
+ (end 138.485 72.539999)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "1db3e63b-d7d3-4271-a9fa-b0796ffa017e")
+ )
+ (segment
+ (start 141.4 113.951471)
+ (end 141.751471 113.6)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "2097ce7d-5890-475c-b829-c5e9a6ea50bc")
+ )
+ (segment
+ (start 136.825 76.248529)
+ (end 138.485 74.588529)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "348f6de3-76c0-42e3-a994-073f34529097")
+ )
+ (segment
+ (start 138.45 118.75)
+ (end 141.4 115.8)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "60dea54a-6440-4d9d-9617-7680300b9486")
+ )
+ (segment
+ (start 136.825 84.840255)
+ (end 136.825 76.248529)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "61817c01-9c98-4fda-b123-3f35bcab8fc6")
+ )
+ (segment
+ (start 140.95 88.965255)
+ (end 136.825 84.840255)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "72b4cbb2-270b-4dba-a8f2-9035c9be5946")
+ )
+ (segment
+ (start 140.95 90.7)
+ (end 140.95 88.965255)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "744df1f1-4804-400b-b298-cc600628305f")
+ )
+ (segment
+ (start 142 113.6)
+ (end 142 107.3)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "7e18483a-dca1-448a-9ddf-87bd9dc36dab")
+ )
+ (segment
+ (start 141.4 115.8)
+ (end 141.4 113.951471)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "829e3cc7-19c8-4b27-92d1-33fc68d49395")
+ )
+ (segment
+ (start 138.2 119.5)
+ (end 138.2 119)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "92c4c6b9-80b2-42e5-836a-57de98955969")
+ )
+ (segment
+ (start 141.751471 113.6)
+ (end 142 113.6)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "b1ee0c93-5f6a-4536-a22f-738e81e468a3")
+ )
+ (segment
+ (start 138.2 119)
+ (end 138.45 118.75)
+ (width 0.2)
+ (layer "F.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "badebe9e-a2fd-4acd-bc7f-5c00aed49c36")
+ )
+ (via
+ (at 140.95 90.7)
+ (size 0.6)
+ (drill 0.3)
+ (layers "F.Cu" "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "01e75d0e-132e-4c32-a7ed-7e79123a0c57")
+ )
+ (via
+ (at 138.485 72.539999)
+ (size 0.6)
+ (drill 0.3)
+ (layers "F.Cu" "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "034ec525-4d56-4b3b-91b8-82fff126752d")
+ )
+ (via
+ (at 142 107.3)
+ (size 0.6)
+ (drill 0.3)
+ (layers "F.Cu" "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "54dfdcc4-7e5a-46db-a25d-9b3f49cfd01b")
+ )
+ (segment
+ (start 142.7 97.6)
+ (end 142.7 93.5)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "09fe6f92-9e04-4ba4-9d03-c073381dc901")
+ )
+ (segment
+ (start 143.2 98.1)
+ (end 142.7 97.6)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "3f31b1e1-abb7-4e71-b528-b60fbe25a48b")
+ )
+ (segment
+ (start 142 107.3)
+ (end 143.2 106.1)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "41733a2e-2396-4c5b-9393-66bf3739c162")
+ )
+ (segment
+ (start 138.385 72.44)
+ (end 138.485 72.539999)
+ (width 0.3)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "59dd0f51-8058-4c5b-bda6-638a82a844c7")
+ )
+ (segment
+ (start 143.2 106.1)
+ (end 143.2 98.1)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "6b699eb9-7b8d-4f12-abba-c838def9d377")
+ )
+ (segment
+ (start 136.935 72.44)
+ (end 138.385 72.44)
+ (width 0.3)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "89103954-78e1-436f-92b5-11159941f3b9")
+ )
+ (segment
+ (start 140.95 91.75)
+ (end 140.95 90.7)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "b6b0213f-7930-422d-abcf-9df4dbf4a136")
+ )
+ (segment
+ (start 142.7 93.5)
+ (end 140.95 91.75)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/MCU_Core/PWR_HOLD")
+ (uuid "c221372f-870c-4836-90f0-577b1e33d84b")
+ )
(segment
(start 137 124.9)
(end 138.379999 124.9)
@@ -36550,6 +36814,14 @@
(net "/Power_Buck/PWR_EN")
(uuid "0bda428c-568f-4e6b-b250-990ae984a606")
)
+ (segment
+ (start 138.175 80.8)
+ (end 138.28 80.8)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Buck/PWR_EN")
+ (uuid "22b66bef-a40a-4e10-9425-e0f4fdf96442")
+ )
(segment
(start 141.643679 81.035)
(end 140.4 81.035)
@@ -36854,6 +37126,14 @@
(net "/Power_Control/PWR_BTN_INV_BASE")
(uuid "b8a0c5e9-6bb5-473e-beca-40fd5eb6d9cf")
)
+ (segment
+ (start 133.389999 77.79)
+ (end 133.384999 76.94)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "02daaab7-9a4e-442e-b583-99867f12d3bf")
+ )
(segment
(start 132.334999 75.44)
(end 132.334999 74.9)
@@ -36870,6 +37150,14 @@
(net "/Power_Control/PWR_LATCH_G")
(uuid "088c97c1-22c7-490e-9713-bdb17d03dbf3")
)
+ (segment
+ (start 135.9 80.8)
+ (end 135.05 79.95)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "17b95c8a-ad8b-4c27-a6f1-8699799d8a88")
+ )
(segment
(start 132.334999 75.889999)
(end 132.334999 76.49)
@@ -36894,6 +37182,14 @@
(net "/Power_Control/PWR_LATCH_G")
(uuid "36b5a79f-36b5-4bb5-a6af-8a47eacdd20f")
)
+ (segment
+ (start 135.05 79.95)
+ (end 133.85 79.95)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "3cd1447b-6982-401a-b1cf-b5179b606324")
+ )
(segment
(start 133.634999 74.59)
(end 133.634999 72.44)
@@ -36902,6 +37198,38 @@
(net "/Power_Control/PWR_LATCH_G")
(uuid "4fbfac4c-3eb0-4089-b696-b7aeaada4cc9")
)
+ (segment
+ (start 133.65 79.75)
+ (end 133.65 78.05)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "5b3670df-b8b4-442b-b61d-2c42f889aab1")
+ )
+ (segment
+ (start 133.65 78.05)
+ (end 133.389999 77.79)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "5d5700a6-09fb-406f-b97b-afba0f9041e0")
+ )
+ (segment
+ (start 133.85 79.95)
+ (end 133.65 79.75)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "5e2f9542-75b0-4d60-95dd-273945ed3acc")
+ )
+ (segment
+ (start 136.625 80.8)
+ (end 135.9 80.8)
+ (width 0.2)
+ (layer "B.Cu")
+ (net "/Power_Control/PWR_LATCH_G")
+ (uuid "a281f902-ecdc-40e5-9772-20a957fe761c")
+ )
(segment
(start 132.785 75.44)
(end 133.634999 74.59)
diff --git a/PCB/v2.x/stackup/board.kdl b/PCB/v2.x/stackup/board.kdl
index 2fce95d..6d01143 100644
--- a/PCB/v2.x/stackup/board.kdl
+++ b/PCB/v2.x/stackup/board.kdl
@@ -61,11 +61,15 @@ design snips_controller {
place resistor "R_FB1" designator="R_FB1" footprint="Resistor_SMD:R_0402_1005Metric" value="255kΩ" bom_value="255kΩ ±1% 62.5mW | RC0402FR-07255KL | Yageo | 0402"
place resistor "R_FB2" designator="R_FB2" footprint="Resistor_SMD:R_0402_1005Metric" value="56.2kΩ" bom_value="56.2kΩ ±1% 62.5mW | RC0402FR-0756K2L | Yageo | 0402"
place resistor "R_GATE1" designator="R_GATE1" footprint="Resistor_SMD:R_0402_1005Metric" value="100kΩ" bom_value="100kΩ ±1% 62.5mW | 0402WGF1003TCE | UNI-ROYAL | 0402"
+ // Gives the latch hysteresis. As PWR_EN falls it kicks the gate down, clear of threshold, so RXD0's pull-up cannot
+ // restart the board when it returns at brownout. It also couples a rising gate back into PWR_EN, which is why
+ // R_PWR_EN_PD1 is 22k: at 100k that alone lifts EN past its threshold. See scripts/spice/latch_v2_sim.py.
+ place capacitor "C_LATCH_FB1" designator="C_LATCH_FB1" footprint="Capacitor_SMD:C_0603_1608Metric" value="470nF" bom_value="470nF 25V X7R ±10% | CL10B474KA8NNNC | Samsung | 0603"
place resistor "R_INV_BASE1" designator="R_INV_BASE1" footprint="Resistor_SMD:R_0402_1005Metric" value="220kΩ" bom_value="220kΩ ±1% 62.5mW | 0402WGF2203TCE | UNI-ROYAL | 0402"
place resistor "R_INV_PU1" designator="R_INV_PU1" footprint="Resistor_SMD:R_0402_1005Metric" value="220kΩ" bom_value="220kΩ ±1% 62.5mW | 0402WGF2203TCE | UNI-ROYAL | 0402"
place resistor "R_ISET1" designator="R_ISET1" footprint="Resistor_SMD:R_0402_1005Metric" value="604Ω" bom_value="604Ω ±1% 62.5mW | AC0402FR-07604RL | Yageo | 0402"
place resistor "R_LATCH_G1" designator="R_LATCH_G1" footprint="Resistor_SMD:R_0402_1005Metric" value="1MΩ" bom_value="1MΩ ±1% 62.5mW | 0402WGF1004TCE | UNI-ROYAL | 0402"
- place pull-down "R_PWR_EN_PD1" designator="R_PWR_EN_PD1" footprint="Resistor_SMD:R_0402_1005Metric" value="100kΩ" bom_value="100kΩ ±1% 62.5mW | 0402WGF1003TCE | UNI-ROYAL | 0402"
+ place pull-down "R_PWR_EN_PD1" designator="R_PWR_EN_PD1" footprint="Resistor_SMD:R_0402_1005Metric" value="22kΩ" bom_value="22kΩ ±1% 62.5mW | 0402WGF2202TCE | UNI-ROYAL | 0402"
place resistor "R_RGB1" designator="R_RGB1" footprint="Resistor_SMD:R_0402_1005Metric" value="470Ω" bom_value="470Ω ±1% 62.5mW | 0402WGF4700TCE | UNI-ROYAL | 0402"
place resistor "R_STAT1" designator="R_STAT1" footprint="Resistor_SMD:R_0402_1005Metric" value="10kΩ" bom_value="10kΩ ±1% 62.5mW | 0402WGF1002TCE | UNI-ROYAL | 0402"
place resistor "R_STAT2" designator="R_STAT2" footprint="Resistor_SMD:R_0402_1005Metric" value="10kΩ" bom_value="10kΩ ±1% 62.5mW | 0402WGF1002TCE | UNI-ROYAL | 0402"
@@ -93,10 +97,10 @@ design snips_controller {
// Reflows on the last pass, on top: Espressif requires a single reflow for the module. The MINI-1U fits the
// 17.5 mm between the macro row and the USB pads, where the 19.2 mm WROOM-1U does not.
// Turned 270 degrees so the signal pins face the stick, the OLED and the carrier, and the GND edge faces the side.
- // Pins are assigned by position, not from V1's map. PWR_HOLD is on IO3, which has no reset pull (ESP32-S3
- // datasheet Table 2-1): RXD0's pull-up could re-latch the board as the rail collapses at power-off. C_LATCH_G1
- // carries the latch through a short reset, and firmware holds the pin with gpio_hold_en for USB uploads. It has
- // to be an RTC pad: on V1 hardware IO3 held through a full upload, and IO42, a digital pad, lost its hold.
+ // Pins are assigned by position, not from V1's map. PWR_HOLD is on RXD0, whose pull-up holds the latch through
+ // any reset or USB upload with no firmware help (ESP32-S3 datasheet Table 2-1). C_LATCH_FB1 keeps that same
+ // pull-up from re-latching the board at power-off. gpio_hold is not an alternative: on V1 hardware IO42's hold
+ // did not survive an upload.
place esp32-s3-mini-1u "U_MCU1" designator="U_MCU1" footprint="Espressif:ESP32-S3-MINI-1U" value="ESP32-S3-MINI-1U-N8" bom_value="Wi-Fi BLE module 8MB flash no PSRAM | ESP32-S3-MINI-1U-N8 | Espressif | SMD module 15.4x15.4mm | N8 variant with external antenna connector"
// Optional XBee 3 daughter board, hand-soldered to these pads by its castellations. It carries the XBee's
// decoupling, the RESET pull-up and RC, and the ATTN/BOOTMODE pull-up, so nothing here depends on it being fitted.
@@ -134,7 +138,7 @@ design snips_controller {
circuit "J_STICK1.p_a" "U_MCU1.IO17" name="/MCU_Core/BTN_STICK"
circuit "R_BOOT_PU1.A" "SW_BOOT1.2" "U_MCU1.IO0" name="/MCU_Core/MCU_BOOT"
circuit "C_DBNC1.A" "D_INV_ISO1.K" "R_BTN_PU1.B" "SW_PWR1.1" "U_MCU1.IO21" name="/MCU_Core/PWR_BTN_SENSE"
- circuit "D_OR2.A" "U_MCU1.IO3" name="/MCU_Core/PWR_HOLD"
+ circuit "D_OR2.A" "U_MCU1.RXD0" name="/MCU_Core/PWR_HOLD"
circuit "R_RGB1.B" "U_MCU1.IO48" name="/MCU_Core/RGB_DIN"
circuit "R_STAT1.A" "U_CHG1.STAT1" "U_MCU1.IO15" name="/MCU_Core/STAT1"
circuit "R_STAT2.A" "U_CHG1.STAT2" "U_MCU1.IO14" name="/MCU_Core/STAT2"
@@ -147,18 +151,18 @@ design snips_controller {
circuit "U_MCU1.IO36" "U_XBEE1.DOUT" name="/XBee/XBEE_DOUT"
circuit "U_MCU1.IO39" "U_XBEE1.RTS" name="/XBee/XBEE_RTS"
circuit "U_MCU1.IO41" "U_XBEE1.ON_SLEEP" name="/XBee/XBEE_ON_SLEEP"
- circuit "U_MCU1.RXD0" "U_XBEE1.RESET" name="/XBee/XBEE_RESET"
+ circuit "U_MCU1.IO42" "U_XBEE1.RESET" name="/XBee/XBEE_RESET"
circuit "U_MCU1.IO1" "U_XBEE1.SLEEP_RQ" name="/XBee/XBEE_SLEEP_RQ"
circuit "R_FB1.A" "R_FB2.A" "U_BUCK1.FB" name="/Power_Buck/BUCK_FB"
circuit "L_BUCK1.A" "U_BUCK1.SW" name="/Power_Buck/BUCK_SW"
- circuit "Q_PWR1.DRAIN" "R_PWR_EN_PD1.node" "U_BUCK1.EN" name="/Power_Buck/PWR_EN"
+ circuit "C_LATCH_FB1.A" "Q_PWR1.DRAIN" "R_PWR_EN_PD1.node" "U_BUCK1.EN" name="/Power_Buck/PWR_EN"
circuit "R_ISET1.A" "U_CHG1.ISET" name="/Power_Charger/CHG_ISET"
circuit "R_TS1.A" "U_CHG1.TS" name="/Power_Charger/CHG_TS"
circuit "R_VSET1.A" "U_CHG1.VSET" name="/Power_Charger/CHG_VSET"
circuit "D_INV_ISO1.A" "Q_INV1.BASE" "R_INV_BASE1.B" name="/Power_Control/PWR_BTN_INV_BASE"
circuit "D_OR1.A" "Q_INV1.COLLECTOR" "R_INV_PU1.B" name="/Power_Control/PWR_BTN_TRIGGER"
circuit "Q_LATCH1.DRAIN" "Q_PWR1.GATE" "R_GATE1.B" name="/Power_Control/PWR_GATE"
- circuit "C_LATCH_G1.B" "D_OR1.K" "D_OR2.K" "Q_LATCH1.GATE" "R_LATCH_G1.B" name="/Power_Control/PWR_LATCH_G"
+ circuit "C_LATCH_FB1.B" "C_LATCH_G1.B" "D_OR1.K" "D_OR2.K" "Q_LATCH1.GATE" "R_LATCH_G1.B" name="/Power_Control/PWR_LATCH_G"
circuit "D_RGB1.DIN" "R_RGB1.A" name="/RGB_LED/RGB_DIN_R"
circuit "J_USB1.CC1" "R_CC1.A" name="/USB_C/USB_CC1"
circuit "J_USB1.CC2" "R_CC2.A" name="/USB_C/USB_CC2"
@@ -174,7 +178,7 @@ design snips_controller {
nc "J_USB1.SBU1"
nc "J_USB1.SBU2"
nc "U_IMU1.INT2"
- nc "U_MCU1.IO42" // no reset pull and free since PWR_HOLD left it: a digital-pad hold does not survive an upload
+ nc "U_MCU1.IO3" // strap: floating is fine, and a load could upset the JTAG source select
nc "U_MCU1.IO45" // strap: stays on its internal pull-down, since high would select 1.8 V flash
nc "U_MCU1.IO46" // strap: stays on its internal pull-down, so no load can disturb the boot mode
nc "U_MCU1.TXD0" // prints the boot log, so it stays free for debugging
@@ -207,6 +211,16 @@ design snips_controller {
when footprint="Capacitor_SMD:C_0402_1005Metric"
set mpn="CL05A105KQ5NNNC"
}
+ match placement {
+ when value="22kΩ"
+ when footprint="Resistor_SMD:R_0402_1005Metric"
+ set mpn="0402WGF2202TCE"
+ }
+ match placement {
+ when value="470nF"
+ when footprint="Capacitor_SMD:C_0603_1608Metric"
+ set mpn="CL10B474KA8NNNC"
+ }
match placement {
when value="220kΩ"
when footprint="Resistor_SMD:R_0402_1005Metric"
diff --git a/PCB/v2.x/stackup/purchasing.kdl b/PCB/v2.x/stackup/purchasing.kdl
index be6a770..e2e22dc 100644
--- a/PCB/v2.x/stackup/purchasing.kdl
+++ b/PCB/v2.x/stackup/purchasing.kdl
@@ -173,6 +173,14 @@ mpn "CL05A105KQ5NNNC" manufacturer="Samsung Electro-Mechanics" value="1µF" foot
catalog lcsc="C107372"
}
+mpn "CL10B474KA8NNNC" manufacturer="Samsung Electro-Mechanics" value="470nF" footprint="Capacitor_SMD:C_0603_1608Metric" rated_voltage="25V" {
+ catalog lcsc="C1623"
+}
+
+mpn "0402WGF2202TCE" manufacturer="UNI-ROYAL(Uniroyal Elec)" value="22kΩ" footprint="Resistor_SMD:R_0402_1005Metric" {
+ catalog lcsc="C25768"
+}
+
mpn "0402WGF2203TCE" manufacturer="UNI-ROYAL(Uniroyal Elec)" value="220kΩ" footprint="Resistor_SMD:R_0402_1005Metric" {
catalog lcsc="C25767"
}
diff --git a/scripts/spice/README.md b/scripts/spice/README.md
index a2070e0..a97562b 100644
--- a/scripts/spice/README.md
+++ b/scripts/spice/README.md
@@ -26,7 +26,7 @@ Set `NGSPICE_LIB` to use a different copy. No Python packages are needed.
## V2
-`latch_v2_sim.py` covers the V2 latch, which differs from V1: PWR_HOLD is on IO3 with no reset pull, C_LATCH_G1 is 1 uF, and R_INV_BASE1 and R_INV_PU1 are 220k. It asserts battery insertion, USB hot-plug with the board off, press time, power-off, riding through a reset (500 ms at 1 uF, 300 ms at an estimated 0.55 uF after bias and tolerance), insertion with the pad ESD diodes into the dead rail, the off drain from the resistors, and a 500 ms press surviving until firmware drives PWR_HOLD 350 ms after the rail comes up. That 350 ms is an estimate until measured. Run it with `python3 scripts/spice/latch_v2_sim.py`. It uses a behavioural buck, and `gpio_hold_en` is firmware, so it is not modeled.
+`latch_v2_sim.py` covers the V2 latch, which differs from V1: C_LATCH_FB1 (470 nF, PWR_EN to gate) gives it hysteresis, R_PWR_EN_PD1 is 22k, C_LATCH_G1 is 1 uF, and R_INV_BASE1 and R_INV_PU1 are 220k. PWR_HOLD is on RXD0, as on V1. It asserts insertion, contact bounce, USB hot-plug, insertion with the pad ESD diodes into the dead rail, the off drain from the resistors, a button knock, press time, a 1 s press holding from the pull-up alone, the hold through an upload, USB pulled while on, power-off with the pull-up returning at 2.0-2.8 V (30k and 100k, 5 and 20 mA), power-off with the button held, and both extremes of the capacitor ratio. Run it with `python3 scripts/spice/latch_v2_sim.py`. It uses a behavioural buck, and the datasheet gives only a typical pull-up, so 30k-100k is a deliberately wide spread. It re-latches the circuit without C_LATCH_FB1 at every load, yet V1 stayed off about 10 of 10 on the bench, so read it as pessimistic.
## Keeping it in sync
diff --git a/scripts/spice/latch_v2_sim.py b/scripts/spice/latch_v2_sim.py
index 881691a..3dafdee 100755
--- a/scripts/spice/latch_v2_sim.py
+++ b/scripts/spice/latch_v2_sim.py
@@ -1,16 +1,23 @@
#!/usr/bin/env python3
-"""ngspice check of the V2 soft latch, which differs from V1 in three ways.
+"""ngspice check of the V2 soft latch across every state it has to survive.
-PWR_HOLD is on IO3, which has no reset pull, so the pin floats during a reset. C_LATCH_G1 is 1 uF so
-the latch rides through a short reset, and R_INV_BASE1 and R_INV_PU1 are 220k to cut the off current.
+PWR_HOLD is on RXD0, whose pull-up holds the latch through any reset and upload with no firmware help. That
+same pull-up comes back as the rail collapses at power-off, and the gate is sitting right at threshold then, so
+a plain latch can restart itself. C_LATCH_FB1, from PWR_EN to the gate, gives the latch hysteresis: as PWR_EN
+falls it kicks the gate down, so the returning pull-up has real ground to make up before the rail is gone.
insert battery plugged in with the board off: the gate stays low
+ bounce the battery contact chatters with the board off: the board stays off
hotplug USB raises VSYS with the board off: the gate stays low
+ clamped battery insertion with the pad ESD diodes into the dead rail: the gate stays low, the drain is bounded
+ bump a 20 ms knock on the button: the board stays off
press a held button turns PWR_EN on, across supply and FET-threshold corners
- off firmware drops PWR_HOLD: PWR_EN falls and stays down, and no pull-up can re-latch it
- ride the hold pin floats for 500 ms (a reset): the board stays on, and for 300 ms at a derated C_LATCH_G1
- clamped battery insertion with the pad ESD diodes into the dead rail: the gate stays low, and the off drain is bounded
- boot a 500 ms press survives until firmware drives PWR_HOLD 350 ms after the rail comes up
+ boot a 1 s press stays on from the pull-up alone: no firmware is running
+ upload the pull-up holds the latch for as long as a reset or upload lasts
+ unplug USB pulled while on: VSYS drops, the kick must not turn the board off
+ off firmware drops PWR_HOLD, then the pull-up returns at a sweep of brownout levels: it stays off
+ offheld the same with the button still held: off comes on release
+ ratio the same as off at both extremes of the two capacitors' ratio
Reuses the models and solver wrapper in latch_sim.py. The netlist mirrors PCB/v2.x/stackup/board.kdl by
hand, so update it when those values or that topology change. See README.md for what is not modeled.
@@ -25,21 +32,24 @@
import latch_sim as ls
R_INV_BASE1 = R_INV_PU1 = "220k"
+R_PWR_EN_PD1 = "22k"
C_LATCH_G1 = "1u"
-C_LATCH_DERATED = "0.55u" # estimate: -10% tolerance and about -40% for a 6.3 V 0402 X5R at 2.8 V bias
+C_LATCH_FB1 = "470n"
+C_FB_LOW = "230n" # estimate: a 16 V X7R at 3.5 V bias and -20%, the case with the least kick
+C_LATCH_LOW = "0.55u" # estimate: -10% tolerance and about -40% for a 6.3 V 0402 X5R at 2.8 V bias
CORNERS = ((3.0, 1.45, 1.3), (3.7, 1.05, 0.9), (4.2, 0.65, 0.6), (4.5, 0.65, 0.6))
+WPU = ("30k", "100k") # the datasheet gives only 45k typical, so this is a deliberately wide spread
+BROWNOUTS = (2.8, 2.4, 2.0) # rail level at which the chip resets and the pull-up returns
MAX_GATE_OFF = 0.5 # V, well under the AO3400A's 0.65 V minimum threshold
-MAX_PRESS_S = 0.25 # button press to PWR_EN on
-MAX_OFF_S = 2.5 # PWR_HOLD low to PWR_EN low
-RIDE_S = 0.5 # reset the latch must ride through
-RIDE_DERATED_S = 0.3 # the same, at C_LATCH_DERATED
+MAX_PRESS_S = 0.5 # button press to PWR_EN on
+MAX_OFF_S = 3.0 # PWR_HOLD low to PWR_EN low
MAX_OFF_DRAIN = 60e-6 # A from VSYS with the board off, resistors only: no IC quiescent current
-PRESS_S = 0.5 # press the board must accept as a normal turn-on
-FW_DELAY_S = 0.35 # rail up to firmware driving PWR_HOLD, an estimate until measured
+BOOT_PRESS_S = 1.0 # press the board must accept as a normal turn-on
+BUMP_S = 0.02 # knock on the button that must not turn the board on
-def core(vthn, vthp, vsys_pwl, sw_pwl, c_latch=C_LATCH_G1):
+def core(vthn, vthp, vsys_pwl, sw_pwl, c_latch=C_LATCH_G1, c_fb=C_LATCH_FB1):
return f"""* v2 latch
.param VTHN={vthn} VTHP={vthp}
{ls.MODELS}
@@ -59,13 +69,14 @@ def core(vthn, vthp, vsys_pwl, sw_pwl, c_latch=C_LATCH_G1):
Dor2 hold latchg D4148
Rlg latchg 0 {ls.R_LATCH_G1}
Clatch latchg 0 {c_latch}
+Cfb pwren latchg {c_fb}
Mlatch pwrgate latchg 0 0 NAO3400 W=1 L=1
Cgs1 latchg 0 550p
Cgd1 latchg pwrgate 75p
Rgate vsys pwrgate {ls.R_GATE1}
Mpwr pwren pwrgate vsys vsys PAO3401 W=1 L=1
Cgs2 pwrgate vsys 500p
-Rpd pwren 0 {ls.R_PWR_EN_PD1}
+Rpd pwren 0 {R_PWR_EN_PD1}
Cen pwren 0 20p
"""
@@ -75,20 +86,21 @@ def buck(vsys, load_a=0.06, c="37u"):
return f"V33 bk 0 {v}\nSbk bk v3v3 pwren 0 SWBK\nCrail v3v3 0 {c}\nRload v3v3 0 {v / load_a}\n"
-def dead_rail():
- return "R3 v3v3 0 300\nC3 v3v3 0 1u\nRh hold 0 100Meg\n"
+def dead_rail(wpu="45k"):
+ return f"R3 v3v3 0 300\nC3 v3v3 0 1u\nRw v3v3 hold {wpu}\n"
def clamped_rail(crail):
- """The dead rail with the ESD diodes of IO21, IO3 and IO10 into it, and the VSYS divider on IO10."""
+ """The dead rail with the ESD diodes of IO21, RXD0 and IO10 into it, and the VSYS divider on IO10."""
return (f"Rv1 vsys io10 200k\nRv2 io10 0 100k\nCv io10 0 100n\nDio10 io10 v3v3 DESD\nDio21 sense v3v3 DESD\n"
- f"Dio42 hold v3v3 DESD\n.model DESD D(IS=1e-14 N=1.05)\nR3 v3v3 0 311k\nC3 v3v3 0 {crail}\nRh hold 0 100Meg\n")
+ f"Dio44 hold v3v3 DESD\n.model DESD D(IS=1e-14 N=1.05)\nR3 v3v3 0 311k\nC3 v3v3 0 {crail}\nRw v3v3 hold 45k\n")
-def firmware(delay):
- """Drives PWR_HOLD from the rail once the rail has been up for delay seconds."""
- return (f"Bup 0 up I = v(v3v3) > 2.8 ? {1e-6 / delay} : 0\nCup up 0 1u\nRup up 0 1G\n"
- "Bhi hi 0 V = v(up) > 1 ? 1 : 0\nSdrv v3v3 hold hi 0 SWDR\nRh hold 0 100Meg\n")
+def shutdown(bod, wpu):
+ """Firmware pulls PWR_HOLD low at 10 ms until the rail reaches bod, when the chip resets and its pull-up returns."""
+ return (f"Bf 0 flag I = (v(v3v3) < {bod} && time > 10m) ? 1m : 0\nCf flag 0 1u\nRf flag 0 1G\n"
+ "Blo lo 0 V = (time >= 10m && v(flag) < 0.5) ? 1 : 0\nSlow hold 0 lo 0 SWDR\n"
+ f"Rw v3v3 hold {wpu}\n")
def run(net, nodes=("v(latchg)", "v(pwren)", "v(v3v3)")):
@@ -105,6 +117,11 @@ def run(net, nodes=("v(latchg)", "v(pwren)", "v(v3v3)")):
return [r[0] for r in rows], {n: [r[2 * i + 1] for r in rows] for i, n in enumerate(names)}
+def hold_ic(v):
+ gate = min(v - 0.7, 2.8)
+ return f".ic v(latchg)={gate} v(v3v3)=3.3 v(sense)=3.3 v(pwren)={v} v(pwrgate)=0 v(base)=0.72 v(trig)=0 v(hold)=3.3\n"
+
+
def insert():
out = []
for (v, n, p), rise in zip(CORNERS, ("1m", "100u", "10u", "10u")):
@@ -114,6 +131,20 @@ def insert():
return out
+def bounce():
+ out = []
+ for v, n, p in CORNERS:
+ steps, t = ["0 0"], 0.0
+ for i in range(8):
+ t += 0.001
+ steps += [f"{t:.4f} {v if i % 2 == 0 else 0}", f"{t + 1e-5:.5f} {0 if i % 2 == 0 else v}"]
+ steps.append(f"1 {0 if len(steps) % 2 == 0 else v}")
+ _, d = run(core(n, p, " ".join(steps), "0 0 1 0") + dead_rail() + ".tran 5u 300m uic\n.end\n")
+ pk = max(d["latchg"])
+ out.append((f"bounce VSYS={v}V", pk < MAX_GATE_OFF and max(d["pwren"]) < 0.4, f"peak gate {pk:.2f} V"))
+ return out
+
+
def hotplug():
out = []
for a in (3.0, 3.7, 4.2):
@@ -125,10 +156,32 @@ def hotplug():
return out
+def clamped():
+ out = []
+ for v in (3.0, 4.2, 4.5):
+ for crail in ("10u", "37u"):
+ net = core(0.65, 0.6, f"0 0 10u {v} 1 {v}", "0 0 1 0") + clamped_rail(crail) + ".tran 20u 600m uic\n.end\n"
+ _, d = run(net, ("v(latchg)", "v(pwren)", "i(Vsys)"))
+ pk, drain = max(d["latchg"]), abs(d["i(Vsys)"][-1])
+ ok = pk < MAX_GATE_OFF and max(d["pwren"]) < 0.4 and drain < MAX_OFF_DRAIN
+ out.append((f"clamped VSYS={v}V rail {crail}", ok, f"peak gate {pk:.2f} V, drain {drain * 1e6:.0f} uA"))
+ return out
+
+
+def bump():
+ out = []
+ for v, n, p in CORNERS:
+ sw = f"0 0 10m 0 10.01m 1 {0.01 + BUMP_S} 1 {0.0101 + BUMP_S} 0 2 0"
+ net = core(n, p, f"0 {v} 2 {v}", sw) + buck(v) + "Rw v3v3 hold 45k\n.tran 100u 1 uic\n.end\n"
+ _, d = run(net)
+ out.append((f"bump VSYS={v}V VthN={n}V", d["pwren"][-1] < 0.4, f"PWR_EN ends {d['pwren'][-1]:.2f} V"))
+ return out
+
+
def press():
out = []
for v, n, p in CORNERS:
- net = core(n, p, f"0 {v} 4 {v}", "0 0 10m 0 10.01m 1 1.9 1") + buck(v) + "Rh hold 0 100Meg\n.tran 100u 2 uic\n.end\n"
+ net = core(n, p, f"0 {v} 4 {v}", "0 0 10m 0 10.01m 1 1.9 1") + buck(v) + "Rw v3v3 hold 100k\n.tran 100u 2 uic\n.end\n"
t, d = run(net)
on = next((t[i] - 0.01 for i in range(len(t)) if t[i] > 0.01 and d["pwren"][i] > ls.V_EN_HIGH), None)
out.append((f"press VSYS={v}V VthN={n}V", on is not None and on <= MAX_PRESS_S,
@@ -136,62 +189,83 @@ def press():
return out
-def hold_ic(v):
- gate = min(v - 0.7, 2.8)
- return f".ic v(latchg)={gate} v(v3v3)=3.3 v(sense)=3.3 v(pwren)={v} v(pwrgate)=0 v(base)=0.72 v(trig)=0 v(hold)=3.3\n"
+def boot():
+ out = []
+ for v, n, p in CORNERS:
+ sw = f"0 0 10m 0 10.01m 1 {0.01 + BOOT_PRESS_S} 1 {0.0101 + BOOT_PRESS_S} 0 4 0"
+ net = core(n, p, f"0 {v} 4 {v}", sw) + buck(v) + "Rw v3v3 hold 100k\n.tran 100u 3 uic\n.end\n"
+ _, d = run(net)
+ out.append((f"boot VSYS={v}V VthN={n}V", d["pwren"][-1] > ls.V_EN_HIGH, f"PWR_EN ends {d['pwren'][-1]:.2f} V"))
+ return out
-def power_off():
+def upload():
out = []
for v, n, p in CORNERS:
- net = (core(n, p, f"0 {v} 6 {v}", "0 0 6 0") + buck(v, 0.02) + "Bhi hi 0 V = time < 10m ? 1 : 0\n"
- "Sdrv v3v3 hold hi 0 SWDR\n" + hold_ic(v) + ".tran 200u 5 uic\n.end\n")
- t, d = run(net)
- off = next((t[i] - 0.01 for i in range(len(t)) if t[i] > 0.01 and d["pwren"][i] < 0.4), None)
- ok = off is not None and off <= MAX_OFF_S and d["pwren"][-1] < 0.4
- out.append((f"off VSYS={v}V VthN={n}V", ok, "never" if off is None else f"PWR_EN low after {off:.2f} s"))
+ net = core(n, p, f"0 {v} 6 {v}", "0 0 6 0") + buck(v) + "Rw v3v3 hold 100k\n" + hold_ic(v) + ".tran 500u 5 uic\n.end\n"
+ _, d = run(net)
+ out.append((f"upload VSYS={v}V", d["pwren"][-1] > ls.V_EN_HIGH and min(d["v3v3"]) > 2.8, f"gate ends {d['latchg'][-1]:.2f} V"))
return out
-def ride():
+def unplug():
out = []
- for c, float_s in ((C_LATCH_G1, RIDE_S), (C_LATCH_DERATED, RIDE_DERATED_S)):
- for v, n, p in CORNERS:
- net = (core(n, p, f"0 {v} 6 {v}", "0 0 6 0", c) + buck(v) + f"Bhi hi 0 V = (time < 10m || time > {0.01 + float_s}) ? 1 : 0\n"
- "Sdrv v3v3 hold hi 0 SWDR\n" + hold_ic(v) + ".tran 200u 2 uic\n.end\n")
- _, d = run(net)
- out.append((f"ride {float_s * 1e3:.0f} ms C={c} VSYS={v}V", d["pwren"][-1] > ls.V_EN_HIGH, f"PWR_EN ends {d['pwren'][-1]:.2f} V"))
+ for b in (3.0, 3.7):
+ pwl = f"0 4.5 20m 4.5 20.05m {b} 1 {b}"
+ net = core(1.45, 1.3, pwl, "0 0 1 0") + buck(4.5) + "Rw v3v3 hold 100k\n" + hold_ic(4.5) + ".tran 20u 300m uic\n.end\n"
+ _, d = run(net)
+ out.append((f"unplug 4.5->{b}V", d["pwren"][-1] > ls.V_EN_HIGH, f"gate low point {min(d['latchg']):.2f} V"))
return out
-def clamped():
+def stays_off(v, n, p, load, wpu, bod, c_latch=C_LATCH_G1, c_fb=C_LATCH_FB1, sw="0 0 6 0"):
+ net = core(n, p, f"0 {v} 6 {v}", sw, c_latch, c_fb) + buck(v, load) + shutdown(bod, wpu) + hold_ic(v) + ".tran 200u 5 uic\n.end\n"
+ t, d = run(net)
+ fell = next((t[i] for i in range(len(t)) if t[i] > 0.01 and d["pwren"][i] < 0.4), None)
+ tail = [g for g, tt in zip(d["latchg"], t) if fell is not None and tt > fell]
+ return fell, d["pwren"][-1] < 0.4, max(tail) if tail else None
+
+
+def power_off():
out = []
- for v in (3.0, 4.2, 4.5):
- for crail in ("10u", "37u"):
- net = core(0.65, 0.6, f"0 0 10u {v} 1 {v}", "0 0 1 0") + clamped_rail(crail) + ".tran 20u 600m uic\n.end\n"
- _, d = run(net, ("v(latchg)", "v(pwren)", "i(Vsys)"))
- pk, drain = max(d["latchg"]), abs(d["i(Vsys)"][-1])
- ok = pk < MAX_GATE_OFF and max(d["pwren"]) < 0.4 and drain < MAX_OFF_DRAIN
- out.append((f"clamped VSYS={v}V rail {crail}", ok, f"peak gate {pk:.2f} V, drain {drain * 1e6:.0f} uA"))
+ for v, n, p in CORNERS[:3]:
+ worst, slowest, ok = -9.0, 0.0, True
+ for load in (0.005, 0.02):
+ for wpu in WPU:
+ for bod in BROWNOUTS:
+ fell, low, pk = stays_off(v, n, p, load, wpu, bod, c_fb=C_FB_LOW)
+ ok = ok and fell is not None and low and fell - 0.01 <= MAX_OFF_S and pk < n
+ worst, slowest = max(worst, pk if pk is not None else 9), max(slowest, fell or 9)
+ out.append((f"off VSYS={v}V VthN={n}V", ok, f"peak gate {worst:.2f} V, off by {slowest:.2f} s"))
return out
-def boot():
+def offheld():
out = []
- for v, n, p in CORNERS:
- sw = f"0 0 10m 0 10.01m 1 {0.01 + PRESS_S} 1 {0.0101 + PRESS_S} 0 4 0"
- net = core(n, p, f"0 {v} 4 {v}", sw) + buck(v) + firmware(FW_DELAY_S) + ".tran 100u 2.5 uic\n.end\n"
- _, d = run(net)
- out.append((f"boot VSYS={v}V VthN={n}V", d["pwren"][-1] > ls.V_EN_HIGH, f"PWR_EN ends {d['pwren'][-1]:.2f} V"))
+ for v, n, p in CORNERS[:3]:
+ # The button is held through shutdown, released at 1 s.
+ fell, low, pk = stays_off(v, n, p, 0.02, "45k", 2.4, sw="0 1 1 1 1.01 0 6 0")
+ ok = fell is not None and low and fell > 1.0 and pk < n
+ out.append((f"offheld VSYS={v}V", ok, "never" if fell is None else f"off at {fell:.2f} s, after release"))
+ return out
+
+
+def ratio():
+ out = []
+ for name, c_latch, c_fb in (("least kick", "1.1u", C_FB_LOW), ("most kick", C_LATCH_LOW, "560n")):
+ for v, n, p in CORNERS[:3]:
+ fell, low, pk = stays_off(v, n, p, 0.005, "30k", 2.8, c_latch, c_fb)
+ ok = fell is not None and low and pk < n
+ out.append((f"ratio {name} VSYS={v}V", ok, "never" if fell is None else f"peak gate {pk:.2f} V, off at {fell:.2f} s"))
return out
def main():
bad = 0
- for s in (insert, hotplug, press, power_off, ride, clamped, boot):
+ for s in (insert, bounce, hotplug, clamped, bump, press, boot, upload, unplug, power_off, offheld, ratio):
for name, ok, note in s():
bad += not ok
- print(f"{'PASS' if ok else 'FAIL'} {name:30} {note}")
+ print(f"{'PASS' if ok else 'FAIL'} {name:36} {note}", flush=True)
print("\nall checks passed" if not bad else f"\n{bad} check(s) failed")
return 1 if bad else 0