diff --git a/PCB/v2.x/GPIO_table.md b/PCB/v2.x/GPIO_table.md
index 3e432b4..b536795 100644
--- a/PCB/v2.x/GPIO_table.md
+++ b/PCB/v2.x/GPIO_table.md
@@ -17,15 +17,15 @@ Pins are chosen by position, not carried over from V1, so V2 needs its own firmw
 
 ## Module rules
 - **Variant:** use the -N8.
-- **Straps:** IO0 is pulled up by R_BOOT_PU1. IO3, IO45 and IO46 are unconnected, so nothing can disturb the boot mode or flash voltage.
+- **Straps:** IO0 is pulled up by R_BOOT_PU1. IO45 and IO46 are unconnected, so nothing can disturb the boot mode or flash voltage. IO3 carries PWR_HOLD: its strap only selects the JTAG source, which is ignored at default eFuses (Table 3-5).
 - **ADC:** analog inputs stay on ADC1 (IO1-IO10), since ADC2 is not usable while the Wi-Fi radio runs, which ESP-NOW needs.
-- **PWR_HOLD is on IO42,** which has no reset pull (ESP32-S3 datasheet Table 2-1). RXD0's pull-up could re-latch the board as the rail collapses at power-off. C_LATCH_G1 (1 µF) carries the latch through a reset of about 300 ms at worst (derated capacitor, flat cell).
-- **Firmware must latch PWR_HOLD with `gpio_hold_en(IO42)` once it has driven it high,** so it survives resets and USB uploads, and must call `gpio_hold_dis(IO42)` before driving it low to power off. Espressif documents hold across chip and system resets; confirm it through ROM download mode on hardware.
+- **PWR_HOLD is on IO3,** which has no reset pull (ESP32-S3 datasheet Table 2-1). RXD0's pull-up could re-latch the board as the rail collapses at power-off. It has to be an RTC pad (IO0-IO21): on V1 hardware IO3's hold lasted through a full USB upload, while IO42, a digital pad, lost its hold on the USB reset that ends an upload. C_LATCH_G1 (1 µF) carries the latch through a reset of about 300 ms at worst (derated capacitor, flat cell).
+- **Firmware must latch PWR_HOLD with `gpio_hold_en(IO3)` once it has driven it high,** so it survives resets and USB uploads, and must call `gpio_hold_dis(IO3)` before driving it low to power off. Light sleep must not release it. The V1 test ran IO3 with no load, so confirm with a real upload at V2 bring-up.
 - **Power button sense stays on an RTC-domain pin.** With the board off, VSYS lifts this node through R_INV_BASE1 and D_INV_ISO1. V1 verified that on a VDD3P3_RTC pin; IO33-IO37 are in the VDD_SPI domain (Table 2-1).
 - **TXD0 (IO43)** prints the boot log, so it stays free for debugging. RGB data has moved off it, so the LED no longer sees that traffic.
-- **Boot glitches:** the low-level power-up glitches on IO1-IO17 (Table 2-2, where IO15 and IO16 appear as XTAL_32K) are 60 µs. Those pins carry only inputs, except IO1 (SLEEP_RQ, where low means awake). XBee RESET is on RXD0, which has no listed glitch.
+- **Boot glitches:** the low-level power-up glitches on IO1-IO17 (Table 2-2, where IO15 and IO16 appear as XTAL_32K) are 60 µs. Those pins carry only inputs, except IO1 (SLEEP_RQ, where low means awake) and IO3 (PWR_HOLD, where D_OR2 blocks a low). XBee RESET is on RXD0, which has no listed glitch.
 - **IO26 stays unconnected.** It is the PSRAM chip-select, and Arduino runs a PSRAM probe at every boot, so it is driven before `setup()`. The probe fails on the -N8, which has no PSRAM, and boot continues.
-- **Do not flash V1 firmware on V2.** It would leave PWR_HOLD unheld on IO42, since V1 holds IO44, and treat other V2 pins as SPI. V2 needs its own pin map.
+- **Do not flash V1 firmware on V2.** It would leave PWR_HOLD unheld on IO3, since V1 holds IO44, and treat other V2 pins as SPI. V2 needs its own pin map.
 - **EN:** 10 kΩ and 1 µF, as Espressif advises (Peripheral Schematics), so EN crosses 0.75 × VDD about 14 ms after the rail is up. V1 has no capacitor.
 - **Pad 61:** the thermal pad is 9 segments, soldered to GND.
 
@@ -64,7 +64,7 @@ Pins are chosen by position, not carried over from V1, so V2 needs its own firmw
 | XBee RTS | IO39 | 35 | Carrier pad 4 |
 | Vol down | IO40 | 36 | Direct, active low, internal pull-up |
 | XBee ON/SLEEP | IO41 | 37 | Carrier pad 5 |
-| Power hold (PWR_HOLD) | IO42 | 38 | Must go high early in boot, then latched with `gpio_hold_en` |
+| Power hold (PWR_HOLD) | IO3 | 7 | Must go high early in boot, then latched with `gpio_hold_en` |
 | XBee RESET | RXD0 (IO44) | 40 | Carrier pad 6. Drive open drain only: low or released. The pull-up is on the carrier, and RXD0's own pull-up is harmless here |
 | Reset | EN | 45 | R_EN_PU1 and C_EN1 only, no button |
 
@@ -92,4 +92,4 @@ Every button wires straight to a module GPIO and to GND, using the internal pull
 OLED 0x3C, ICM-42670-P 0x68. R_I2C_SDA1 and R_I2C_SCL1 stay on the board so the IMU works with no OLED attached.
 
 ## Free pins
-TXD0 (IO43) is free. Leave IO26 unconnected (see Module rules). IO3, IO45 and IO46 are straps, so leave them unconnected.
+TXD0 (IO43) and IO42 are free. Leave IO26 unconnected (see Module rules). IO45 and IO46 are straps, so leave them unconnected.
diff --git a/PCB/v2.x/README.md b/PCB/v2.x/README.md
index af32f25..36b2799 100644
--- a/PCB/v2.x/README.md
+++ b/PCB/v2.x/README.md
@@ -16,7 +16,7 @@ through `snips_controller.stackup_sch`; sync it with the Stackup KiCad plugin. R
 - **Reflow:** the bottom side goes first and the top side last, because Espressif requires a single reflow for the module (datasheet section 12.3). The XBee reflows on its own carrier and never goes upside down, which is what stopped the two modules from sharing this board before.
 - **Radio link:** Amidala's droids use XBee Zigbee 3.0, so a Zigbee controller needs the carrier. The firmware still has to move from the XBee's SPI interface to UART, and needs a V2 pin map.
 - **Programming:** USB, through the module's native USB. To force download mode, hold SW_BOOT1 while pressing the power button. A blank board has no firmware to latch PWR_HOLD, so hold the power button through its first flash. After that, uploads need no button.
-- **No reset button:** the power button can only turn the board on. PWR_HOLD is on IO42, which has no reset pull, and C_LATCH_G1 (1 µF) carries the latch through a reset of about 300 ms at worst (derated capacitor, flat cell). Firmware latches the pin with `gpio_hold_en`, so a longer reset or a USB upload holds power with no button, and releases it with `gpio_hold_dis` to power off. Keep a watchdog running to recover from a hang.
+- **No reset button:** the power button can only turn the board on. PWR_HOLD is on IO3, an RTC pad with no reset pull, and C_LATCH_G1 (1 µF) carries the latch through a reset of about 300 ms at worst (derated capacitor, flat cell). Firmware latches the pin with `gpio_hold_en`, so a longer reset or a USB upload holds power with no button, and releases it with `gpio_hold_dis` to power off. Keep a watchdog running to recover from a hang.
 - **Buttons:** all 13 connect directly to module GPIOs. See `GPIO_table.md`.
 - **Power blocks:** the buck, charger and power latch follow V1's relative placement, all on the bottom. Two charger GND vias were moved 0.1-0.75 mm in V1's layout to clear earlier button positions. C_BUCK_IN1 turned 90 degrees with its VSYS pad straight above the VIN pin. BUCK_FB runs around the input cap and hops to F.Cu past the inductor, so both planes shield it; keep it out from under L_BUCK1. The latch is too long to fit whole, so it is split at `PWR_BTN_TRIGGER`: the switch and `PWR_LATCH_G` node sit under the stick, turned 270 degrees, and the inverter sits beside the stick's lower pins. See `diagrams/` for why they are arranged this way.
 - **OLED cable:** U_OLED1's opening faces USB, and a Qwiic plug is 7.0 mm wide with its protrusions, so keep top-side parts out of x 0.9-7.9 mm from the mouth at y 52.7 mm down to the MH3 post. Check that a real cable goes in before committing the shell.
@@ -108,7 +108,7 @@ The droids use XBee Zigbee 3.0, so the controller joins that network through the
 Recommended bringup order:
 1. Current-limited supply on VSYS, with no carrier fitted: check 3V3 and idle current with the power button held.
 2. Flash over USB, holding the power button, with SW_BOOT1 held if the chip does not enumerate. Confirm firmware drives `PWR_HOLD` high.
-3. Time the shortest press that stays on, at 3.3 V and 4.2 V. The simulation gives 0.1-0.2 s on a normal cell and up to about 0.4 s on a flat one, set by when firmware drives `PWR_HOLD`, so plan on a half-second press and keep that drive early in boot. Run a USB upload with no button held, then confirm a watchdog reset reboots the board and a graceful shutdown stays off.
+3. Time the shortest press that stays on, at 3.3 V and 4.2 V. The simulation gives 0.1-0.2 s on a normal cell and up to about 0.4 s on a flat one, set by when firmware drives `PWR_HOLD`, so plan on a half-second press and keep that drive early in boot. Run a USB upload with no button held, which is the first test of IO3's hold under D_OR2's load, then confirm a watchdog reset reboots the board and a graceful shutdown stays off.
 4. OLED and ICM-42670-P on I2C.
 5. SK6812 RGB LED.
 6. Buttons, using the pin table.
@@ -122,8 +122,8 @@ Recommended bringup order:
 
 - Battery → bq25185 (charger and power path, 4.2V, 500mA) → TLV62569 (3.3V buck) → 3V3 for everything, including the carrier.
 - Power switch: soft latch (AO3401A PFET + AO3400A NFET) controls the TLV62569 EN pin. USB does not hold it on.
-- Boot: press the power button → latch enables 3V3 → module boots → IO42 goes high through D_OR2 to hold the latch, then firmware latches it with `gpio_hold_en`.
-- Shutdown: firmware sees a hold on IO21 → graceful shutdown → `gpio_hold_dis`, IO42 low → the gate decays through R_LATCH_G1 in about 0.6-1.7 s → power cut.
+- Boot: press the power button → latch enables 3V3 → module boots → IO3 goes high through D_OR2 to hold the latch, then firmware latches it with `gpio_hold_en`.
+- Shutdown: firmware sees a hold on IO21 → graceful shutdown → `gpio_hold_dis`, IO3 low → the gate decays through R_LATCH_G1 in about 0.6-1.7 s → power cut.
 - bq25185 STAT1 and STAT2 go to IO15 and IO14 (open drain, 10kΩ pull-ups to 3V3).
 - Battery voltage: VSYS through R_VSYS1/R_VSYS2 to IO7, reading VSYS/3.
 - Below about 3.3 V on the battery the buck passes it through, and the DRV5055's minimum is 3.0 V, so the firmware cutoff should sit above that.
diff --git a/PCB/v2.x/diagrams/power_control_layout.md b/PCB/v2.x/diagrams/power_control_layout.md
index cc4d9b3..ff57b50 100644
--- a/PCB/v2.x/diagrams/power_control_layout.md
+++ b/PCB/v2.x/diagrams/power_control_layout.md
@@ -47,7 +47,7 @@ Top copper layer. The VSYS→PWR_EN path runs straight across the top as one thi
 | **B** | **SW_PWR1's position isn't yours to optimize electrically.** It has to land under a hole in whatever enclosure this board sits in — mechanical placement drives this part, and the rest of the latch logic has to route to wherever that ends up, not the other way around. |
 | **C** | **C_DBNC1 sits right on the switch's own pins.** Same principle as the charger's pushbutton guidance in its own datasheet: the debounce cap does its job by being close to the contact bounce it's filtering, not by being close to anything else. |
 | **D** | **The diode-OR and its pull-down are one compact decision node — and R_LATCH_G1's value is load-bearing, not incidental.** D_OR1, D_OR2, R_LATCH_G1, and Q_LATCH1's gate all meet at PWR_LATCH_G. A press only drives this node through `R_INV_PU1` (100kΩ) and a diode drop — with the original 10kΩ pull-down, that divider left barely 0.3V at Q_LATCH1's gate, nowhere near enough to turn it on. Raised to 1MΩ, the same divider delivers ~2.4V at the bottom of the battery range (VSYS≈3.0V, modelling a real ~0.35V diode drop at µA currents) up to ~3.5V at full charge, without adding any idle current (that's set by `R_INV_PU1`, untouched). A 2N7002's worst-case threshold is 2.5V, which left no margin at the bottom, so `Q_LATCH1` is an AO3400A (Vgs(th) ≤1.45V): at least ~1V of overdrive everywhere. Keeping this cluster tight matters less for noise than for just keeping the logic legible on the board. |
-| **E** | **PWR_HOLD arriving late is a hard failure, not a glitch.** Per this project's own GPIO notes, IO42 (PWR_HOLD) must go high as the MCU's very first instruction — release the button before that happens and R_LATCH_G1's pull-down turns everything back off. Not a layout fix, but it's the reason D_OR2's path exists at all. |
+| **E** | **PWR_HOLD arriving late is a hard failure, not a glitch.** Per this project's own GPIO notes, IO3 (PWR_HOLD) must go high as the MCU's very first instruction — release the button before that happens and R_LATCH_G1's pull-down turns everything back off. Not a layout fix, but it's the reason D_OR2's path exists at all. |
 | **F** | **D_OR1 can't read `PWR_BTN_SENSE` directly — found the hard way, on real hardware.** The original design had `R_BTN_PU1` (to VSYS) and a since-removed `R_PWR_SENSE1` (to GND) both on that node, dividing it to roughly half VSYS at idle — comfortably above a diode's ~0.6V forward threshold, so `D_OR1` was forward-biased (and the board powered on) the instant a battery was plugged in, button or no button. The inverter fixes this properly instead of just retuning the divider: idle, `Q_INV1` is on and holds `PWR_BTN_TRIGGER` at GND; pressed, it turns off and `R_INV_PU1` pulls `PWR_BTN_TRIGGER` to VSYS. Only a real press can forward-bias `D_OR1` now. Keep this block close to `D_OR1` — it's parts serving one signal, not worth spreading out.<br><br>**Second-order bug, found the same way:** the inverter's own base resistor originally tapped `PWR_BTN_SENSE` directly, in series with `R_BTN_PU1` — stealing enough idle base current to sag the MCU's own button-read node to ~1V instead of near-VSYS. `R_INV_BASE1` is now its own dedicated 100kΩ pull-up straight to VSYS (not sharing current with `R_BTN_PU1`), and `D_INV_ISO1` (a Schottky, chosen specifically for its lower forward drop than Q_INV1's own base-emitter junction) lets a press still pull the base low without ever loading `PWR_BTN_SENSE`. |
 | **G** | **`PWR_EN` had no defined rest state — TI's own datasheet says not to do this.** `Q_PWR1`'s drain feeds the buck's EN pin directly, with nothing else on that node. TLV62569's EN pin is a bare comparator input with no internal pull ("Do not leave floating" per its datasheet) — with `Q_PWR1` off, EN was held by MOSFET/input leakage alone, no guaranteed logic level. `R_PWR_EN_PD1` (100kΩ to GND) fixes it: negligible loading when `Q_PWR1`'s tens-of-mΩ RDS(on) is driving EN high, solid GND the instant it's off. |
 | **H** | **`PWR_BTN_SENSE` must never sit above the MCU's rail.** It lands directly on IO21 (module pin 25), whose ceiling is VDD + 0.3V (~3.6V), but `R_BTN_PU1` used to pull it to VSYS — up to ~4.5V on USB, and it back-fed the unpowered 3V3 rail through the pin's clamp diode whenever the MCU was off. Since `R_INV_BASE1` gave the inverter its own VSYS pull-up (callout F), `R_BTN_PU1` no longer has to supply the inverter, so it now pulls to 3V3: idle reads 3.3V, and with the MCU off the node is simply unpowered instead of leaking into the rail. |
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
index 057a164..28ced3f 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L4,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
@@ -798,6 +798,10 @@ X122700000Y-114100000D03*
 X121100000Y-124880210D03*
 %TO.N,/XBee/XBEE_SLEEP_RQ*%
 X138900000Y-106200000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO5*%
 X133300000Y-100800000D03*
 X133100000Y-107000000D03*
@@ -842,10 +846,6 @@ X147700000Y-98600000D03*
 X134700000Y-117700000D03*
 %TO.N,/XBee/XBEE_ON_SLEEP*%
 X135600000Y-118300000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
 %TO.N,/XBee/XBEE_RESET*%
 X138200000Y-120550000D03*
 %TO.N,VBUS*%
@@ -1309,6 +1309,27 @@ X139150000Y-105950000D02*
 X139150000Y-103600000D01*
 X138900000Y-106200000D02*
 X139150000Y-105950000D01*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X142700000Y-97600000D02*
+X142700000Y-93500000D01*
+X143200000Y-98100000D02*
+X142700000Y-97600000D01*
+X142000000Y-107300000D02*
+X143200000Y-106100000D01*
+D48*
+X138385000Y-72440000D02*
+X138485000Y-72539999D01*
+D49*
+X143200000Y-106100000D02*
+X143200000Y-98100000D01*
+D48*
+X136935000Y-72440000D02*
+X138385000Y-72440000D01*
+D49*
+X140950000Y-91750000D02*
+X140950000Y-90700000D01*
+X142700000Y-93500000D02*
+X140950000Y-91750000D01*
 %TO.N,/Buttons_Direct/BTN_MACRO5*%
 X135460000Y-102100000D02*
 X135460000Y-101840000D01*
@@ -1516,27 +1537,6 @@ X135600000Y-118300000D02*
 X136610000Y-119310000D01*
 X136610000Y-119310000D02*
 X136610000Y-121300000D01*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X142700000Y-97600000D02*
-X142700000Y-93500000D01*
-X143200000Y-98100000D02*
-X142700000Y-97600000D01*
-X142000000Y-107300000D02*
-X143200000Y-106100000D01*
-D48*
-X138385000Y-72440000D02*
-X138485000Y-72539999D01*
-D49*
-X143200000Y-106100000D02*
-X143200000Y-98100000D01*
-D48*
-X136935000Y-72440000D02*
-X138385000Y-72440000D01*
-D49*
-X140950000Y-91750000D02*
-X140950000Y-90700000D01*
-X142700000Y-93500000D02*
-X140950000Y-91750000D01*
 %TO.N,/XBee/XBEE_RESET*%
 X138200000Y-120550000D02*
 X139150000Y-120550000D01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
index cb1631b..649bea5 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Mask.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Soldermask,Bot*%
 %TF.FilePolarity,Negative*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
index 668e21c..0adf3f9 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Paste.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Paste,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr b/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
index b2240f8..1190789 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-B_Silkscreen.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Legend,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr b/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
index d184bae..45aeb05 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-Edge_Cuts.gbr
@@ -1,11 +1,11 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Profile,NP*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
index a8beec3..e865076 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L1,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
@@ -366,7 +366,7 @@ X139050000Y-105500000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO6*%
 X138200000Y-105500000D03*
 %TO.P,U_MCU1,7*%
-%TO.N,N/C*%
+%TO.N,/MCU_Core/PWR_HOLD*%
 X137350000Y-105500000D03*
 %TO.P,U_MCU1,8*%
 %TO.N,/Buttons_Direct/BTN_MACRO3*%
@@ -461,10 +461,9 @@ X134800000Y-119500000D03*
 %TO.N,/XBee/XBEE_ON_SLEEP*%
 X135650000Y-119500000D03*
 %TO.P,U_MCU1,38*%
-%TO.N,/MCU_Core/PWR_HOLD*%
+%TO.N,N/C*%
 X136500000Y-119500000D03*
 %TO.P,U_MCU1,39*%
-%TO.N,N/C*%
 X137350000Y-119500000D03*
 %TO.P,U_MCU1,40*%
 %TO.N,/XBee/XBEE_RESET*%
@@ -902,6 +901,10 @@ X122700000Y-114100000D03*
 X121100000Y-124880210D03*
 %TO.N,/XBee/XBEE_SLEEP_RQ*%
 X138900000Y-106200000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO5*%
 X133300000Y-100800000D03*
 X133100000Y-107000000D03*
@@ -946,10 +949,6 @@ X147700000Y-98600000D03*
 X134700000Y-117700000D03*
 %TO.N,/XBee/XBEE_ON_SLEEP*%
 X135600000Y-118300000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
 %TO.N,/XBee/XBEE_RESET*%
 X138200000Y-120550000D03*
 %TO.N,VBUS*%
@@ -1564,6 +1563,27 @@ X139050000Y-106050000D02*
 X138900000Y-106200000D01*
 X139050000Y-105500000D02*
 X139050000Y-106050000D01*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X138485000Y-74588529D02*
+X138485000Y-72539999D01*
+X136825000Y-76248529D02*
+X138485000Y-74588529D01*
+X137650000Y-106400000D02*
+X138650000Y-107400000D01*
+X137650000Y-105800000D02*
+X137650000Y-106400000D01*
+X136825000Y-84840255D02*
+X136825000Y-76248529D01*
+X137350000Y-105500000D02*
+X137650000Y-105800000D01*
+X141900000Y-107400000D02*
+X142000000Y-107300000D01*
+X140950000Y-88965255D02*
+X136825000Y-84840255D01*
+X140950000Y-90700000D02*
+X140950000Y-88965255D01*
+X138650000Y-107400000D02*
+X141900000Y-107400000D01*
 %TO.N,/MCU_Core/STICK_Y*%
 X131400000Y-93051471D02*
 X133948529Y-93051471D01*
@@ -1896,31 +1916,6 @@ X135650000Y-118350000D02*
 X135600000Y-118300000D01*
 X135650000Y-119500000D02*
 X135650000Y-118350000D01*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X138485000Y-74588529D02*
-X138485000Y-72539999D01*
-X141400000Y-113951471D02*
-X141751471Y-113600000D01*
-X136825000Y-76248529D02*
-X138485000Y-74588529D01*
-X136500000Y-119500000D02*
-X136500000Y-118750000D01*
-X138450000Y-118750000D02*
-X141400000Y-115800000D01*
-X136825000Y-84840255D02*
-X136825000Y-76248529D01*
-X140950000Y-88965255D02*
-X136825000Y-84840255D01*
-X140950000Y-90700000D02*
-X140950000Y-88965255D01*
-X142000000Y-113600000D02*
-X142000000Y-107300000D01*
-X141400000Y-115800000D02*
-X141400000Y-113951471D01*
-X141751471Y-113600000D02*
-X142000000Y-113600000D01*
-X136500000Y-118750000D02*
-X138450000Y-118750000D01*
 %TO.N,/XBee/XBEE_RESET*%
 X138200000Y-119500000D02*
 X138200000Y-120550000D01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
index f8a9fa9..a1cb87f 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Mask.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Soldermask,Top*%
 %TF.FilePolarity,Negative*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
index bc5d1f9..97eefb5 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Paste.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Paste,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr b/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
index 5cb8289..004d62f 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-F_Silkscreen.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Legend,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
index 7a9f192..d3eb398 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-In1_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L2,Inr*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
@@ -197,6 +197,10 @@ X122700000Y-114100000D03*
 X121100000Y-124880210D03*
 %TO.N,/XBee/XBEE_SLEEP_RQ*%
 X138900000Y-106200000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO5*%
 X133300000Y-100800000D03*
 X133100000Y-107000000D03*
@@ -241,10 +245,6 @@ X147700000Y-98600000D03*
 X134700000Y-117700000D03*
 %TO.N,/XBee/XBEE_ON_SLEEP*%
 X135600000Y-118300000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
 %TO.N,/XBee/XBEE_RESET*%
 X138200000Y-120550000D03*
 %TO.N,VBUS*%
diff --git a/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr b/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
index 8ca64cb..eb8a509 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
+++ b/PCB/v2.x/production/gerbers/snips_controller-In2_Cu.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:19-08:00*%
+%TF.CreationDate,2026-11-01T11:07:59-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Copper,L3,Inr*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:19*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:07:59*
 %MOMM*%
 %LPD*%
 G01*
@@ -197,6 +197,10 @@ X122700000Y-114100000D03*
 X121100000Y-124880210D03*
 %TO.N,/XBee/XBEE_SLEEP_RQ*%
 X138900000Y-106200000D03*
+%TO.N,/MCU_Core/PWR_HOLD*%
+X140950000Y-90700000D03*
+X138485000Y-72539999D03*
+X142000000Y-107300000D03*
 %TO.N,/Buttons_Direct/BTN_MACRO5*%
 X133300000Y-100800000D03*
 X133100000Y-107000000D03*
@@ -241,10 +245,6 @@ X147700000Y-98600000D03*
 X134700000Y-117700000D03*
 %TO.N,/XBee/XBEE_ON_SLEEP*%
 X135600000Y-118300000D03*
-%TO.N,/MCU_Core/PWR_HOLD*%
-X140950000Y-90700000D03*
-X138485000Y-72539999D03*
-X142000000Y-107300000D03*
 %TO.N,/XBee/XBEE_RESET*%
 X138200000Y-120550000D03*
 %TO.N,VBUS*%
diff --git a/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl b/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
index 9a12dbc..2a7e9f0 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
+++ b/PCB/v2.x/production/gerbers/snips_controller-NPTH.drl
@@ -1,7 +1,7 @@
 M48
-; DRILL file KiCad 10.0.5 date 2026-11-01T10:03:20
+; DRILL file KiCad 10.0.5 date 2026-11-01T11:07:59
 ; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-11-01T10:03:20-08:00
+; #@! TF.CreationDate,2026-11-01T11:07:59-08:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
 ; #@! TF.FileFunction,NonPlated,1,4,NPTH
 FMAT,2
diff --git a/PCB/v2.x/production/gerbers/snips_controller-PTH.drl b/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
index fbf56c9..9d4c954 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
+++ b/PCB/v2.x/production/gerbers/snips_controller-PTH.drl
@@ -1,7 +1,7 @@
 M48
-; DRILL file KiCad 10.0.5 date 2026-11-01T10:03:20
+; DRILL file KiCad 10.0.5 date 2026-11-01T11:07:59
 ; FORMAT={-:-/ absolute / metric / decimal}
-; #@! TF.CreationDate,2026-11-01T10:03:20-08:00
+; #@! TF.CreationDate,2026-11-01T11:07:59-08:00
 ; #@! TF.GenerationSoftware,Kicad,Pcbnew,10.0.5
 ; #@! TF.FileFunction,Plated,1,4,PTH
 FMAT,2
diff --git a/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob b/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
index 1197070..d796eec 100644
--- a/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
+++ b/PCB/v2.x/production/gerbers/snips_controller-job.gbrjob
@@ -5,7 +5,7 @@
       "Application": "Pcbnew",
       "Version": "10.0.5"
     },
-    "CreationDate": "2026-11-01T10:03:19-08:00"
+    "CreationDate": "2026-11-01T11:07:59-08:00"
   },
   "GeneralSpecs": {
     "ProjectId": {
diff --git a/PCB/v2.x/production/gerbers/snips_controller.zip b/PCB/v2.x/production/gerbers/snips_controller.zip
index 7f61d5e..fc8e74f 100644
Binary files a/PCB/v2.x/production/gerbers/snips_controller.zip and b/PCB/v2.x/production/gerbers/snips_controller.zip differ
diff --git a/PCB/v2.x/production/jlcpcb/Snips_2_0.zip b/PCB/v2.x/production/jlcpcb/Snips_2_0.zip
index f4111c9..d16b27c 100644
Binary files a/PCB/v2.x/production/jlcpcb/Snips_2_0.zip and b/PCB/v2.x/production/jlcpcb/Snips_2_0.zip differ
diff --git a/PCB/v2.x/production/jlcpcb/netlist.ipc b/PCB/v2.x/production/jlcpcb/netlist.ipc
index 6d12790..5049bc2 100644
--- a/PCB/v2.x/production/jlcpcb/netlist.ipc
+++ b/PCB/v2.x/production/jlcpcb/netlist.ipc
@@ -77,6 +77,9 @@ P  arrayDim   N
 317OMETER/I2C_SCL   VIA        MD0118PA00X+048307Y-044921X0236Y0000R000S3
 317OMETER/I2C_SCL   VIA        MD0118PA00X+047677Y-049165X0236Y0000R000S3
 317/XBEE_SLEEP_RQ   VIA        MD0118PA00X+054685Y-041811X0236Y0000R000S3
+317_CORE/PWR_HOLD   VIA        MD0118PA00X+055492Y-035709X0236Y0000R000S3
+317_CORE/PWR_HOLD   VIA        MD0118PA00X+054522Y-028559X0236Y0000R000S3
+317_CORE/PWR_HOLD   VIA        MD0118PA00X+055906Y-042244X0236Y0000R000S3
 317ECT/BTN_MACRO5   VIA        MD0118PA00X+052480Y-039685X0236Y0000R000S3
 317ECT/BTN_MACRO5   VIA        MD0118PA00X+052402Y-042126X0236Y0000R000S3
 317ECT/BTN_MACRO5   VIA        MD0118PA00X+053607Y-039818X0236Y0000R000S3
@@ -106,9 +109,6 @@ P  arrayDim   N
 317ECT/BTN_VOL_DN   VIA        MD0118PA00X+058150Y-038819X0236Y0000R000S3
 317ECT/BTN_VOL_DN   VIA        MD0118PA00X+053031Y-046339X0236Y0000R000S3
 317/XBEE_ON_SLEEP   VIA        MD0118PA00X+053386Y-046575X0236Y0000R000S3
-317_CORE/PWR_HOLD   VIA        MD0118PA00X+055492Y-035709X0236Y0000R000S3
-317_CORE/PWR_HOLD   VIA        MD0118PA00X+054522Y-028559X0236Y0000R000S3
-317_CORE/PWR_HOLD   VIA        MD0118PA00X+055906Y-042244X0236Y0000R000S3
 317BEE/XBEE_RESET   VIA        MD0118PA00X+054409Y-047461X0236Y0000R000S3
 317VBUS             VIA        MD0118PA00X+049114Y-037516X0236Y0000R000S3
 317VBUS             VIA        MD0118PA00X+048307Y-040201X0236Y0000R000S3
@@ -195,7 +195,7 @@ P  arrayDim   N
 327_CORE/MCU_BOOT   U_MCU1-4          A01X+055079Y-041535X0157Y0315R000S2
 327/XBEE_SLEEP_RQ   U_MCU1-5          A01X+054744Y-041535X0157Y0315R000S2
 327ECT/BTN_MACRO6   U_MCU1-6          A01X+054409Y-041535X0157Y0315R000S2
-327N/C              U_MCU1-7          A01X+054075Y-041535X0157Y0315R000S2
+327_CORE/PWR_HOLD   U_MCU1-7          A01X+054075Y-041535X0157Y0315R000S2
 327ECT/BTN_MACRO3   U_MCU1-8          A01X+053740Y-041535X0157Y0315R000S2
 327ECT/BTN_MACRO2   U_MCU1-9          A01X+053406Y-041535X0157Y0315R000S2
 327U_CORE/STICK_Y   U_MCU1-10         A01X+053071Y-041535X0157Y0315R000S2
@@ -226,7 +226,7 @@ P  arrayDim   N
 327/XBEE/XBEE_RTS   U_MCU1-35         A01X+052736Y-047047X0157Y0315R000S2
 327ECT/BTN_VOL_DN   U_MCU1-36         A01X+053071Y-047047X0157Y0315R000S2
 327/XBEE_ON_SLEEP   U_MCU1-37         A01X+053406Y-047047X0157Y0315R000S2
-327_CORE/PWR_HOLD   U_MCU1-38         A01X+053740Y-047047X0157Y0315R000S2
+327N/C              U_MCU1-38         A01X+053740Y-047047X0157Y0315R000S2
 327N/C              U_MCU1-39         A01X+054075Y-047047X0157Y0315R000S2
 327BEE/XBEE_RESET   U_MCU1-40         A01X+054409Y-047047X0157Y0315R000S2
 327N/C              U_MCU1-41         A01X+054744Y-047047X0157Y0315R000S2
diff --git a/PCB/v2.x/production/placement/snips_controller-all.pos b/PCB/v2.x/production/placement/snips_controller-all.pos
index 84da368..daf9f1b 100644
--- a/PCB/v2.x/production/placement/snips_controller-all.pos
+++ b/PCB/v2.x/production/placement/snips_controller-all.pos
@@ -1,4 +1,4 @@
-### Footprint positions - created on 2026-11-01T10:03:20 ###
+### Footprint positions - created on 2026-11-01T11:07:59 ###
 ### Printed by KiCad version 10.0.5
 ## Unit = mm, Angle = deg.
 ## Side : All
diff --git a/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr b/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
index 85c7e62..1c9ee0c 100644
--- a/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
+++ b/PCB/v2.x/production/placement/snips_controller-pnp_bottom.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:21-08:00*%
+%TF.CreationDate,2026-11-01T11:08:00-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Component,L4,Bot*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:21*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:08:00*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr b/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
index 3f78d7b..b820cc1 100644
--- a/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
+++ b/PCB/v2.x/production/placement/snips_controller-pnp_top.gbr
@@ -1,12 +1,12 @@
 %TF.GenerationSoftware,KiCad,Pcbnew,10.0.5*%
-%TF.CreationDate,2026-11-01T10:03:20-08:00*%
+%TF.CreationDate,2026-11-01T11:08:00-08:00*%
 %TF.ProjectId,snips_controller,736e6970-735f-4636-9f6e-74726f6c6c65,rev?*%
 %TF.SameCoordinates,Original*%
 %TF.FileFunction,Component,L1,Top*%
 %TF.FilePolarity,Positive*%
 %FSLAX46Y46*%
 G04 Gerber Fmt 4.6, Leading zero omitted, Abs format (unit mm)*
-G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 10:03:20*
+G04 Created by KiCad (PCBNEW 10.0.5) date 2026-11-01 11:08:00*
 %MOMM*%
 %LPD*%
 G01*
diff --git a/PCB/v2.x/snips_controller.kicad_pcb b/PCB/v2.x/snips_controller.kicad_pcb
index 97e1921..9744236 100644
--- a/PCB/v2.x/snips_controller.kicad_pcb
+++ b/PCB/v2.x/snips_controller.kicad_pcb
@@ -1882,7 +1882,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:107"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:108"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -4852,7 +4852,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:110"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:111"
 			(at 0 2 0)
 			(layer "F.SilkS")
 			(hide yes)
@@ -5725,7 +5725,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:99"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:100"
 			(at 0 -2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -5988,6 +5988,7 @@
 			(at -7 -0.85)
 			(size 0.4 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
+			(net "/MCU_Core/PWR_HOLD")
 			(uuid "875768b4-6053-4494-8588-1ade1ee79bbe")
 		)
 		(pad "8" smd rect
@@ -6203,7 +6204,6 @@
 			(at 7 0)
 			(size 0.4 0.8)
 			(layers "F.Cu" "F.Mask" "F.Paste")
-			(net "/MCU_Core/PWR_HOLD")
 			(uuid "058f594b-a9c1-4900-8375-c0b6f857f603")
 		)
 		(pad "39" smd rect
@@ -8824,7 +8824,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:104"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:105"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -9920,7 +9920,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:103"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:104"
 			(at 0 2 90)
 			(layer "F.SilkS")
 			(hide yes)
@@ -18497,7 +18497,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:109"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:110"
 			(at 0 -2 90)
 			(layer "B.SilkS")
 			(hide yes)
@@ -25785,7 +25785,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:102"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:103"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -27472,7 +27472,7 @@
 				)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:108"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:109"
 			(at 0 -2 180)
 			(layer "B.SilkS")
 			(hide yes)
@@ -28390,7 +28390,7 @@
 				(justify mirror)
 			)
 		)
-		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:106"
+		(property "Stackup Source" "PCB/v2.x/stackup/board.kdl:107"
 			(at 0 -2 270)
 			(layer "B.SilkS")
 			(hide yes)
@@ -33086,6 +33086,174 @@
 		(net "/XBee/XBEE_SLEEP_RQ")
 		(uuid "7e57f38d-a598-416e-86e2-ec7774bbd1f0")
 	)
+	(segment
+		(start 138.485 74.588529)
+		(end 138.485 72.539999)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "1db3e63b-d7d3-4271-a9fa-b0796ffa017e")
+	)
+	(segment
+		(start 136.825 76.248529)
+		(end 138.485 74.588529)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "348f6de3-76c0-42e3-a994-073f34529097")
+	)
+	(segment
+		(start 137.65 106.4)
+		(end 138.65 107.4)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "46b8ffd9-ea1b-41dc-9cd4-f618d095da8f")
+	)
+	(segment
+		(start 137.65 105.8)
+		(end 137.65 106.4)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "604c8aa3-6520-4ac3-99f9-31d1fb6e943e")
+	)
+	(segment
+		(start 136.825 84.840255)
+		(end 136.825 76.248529)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "61817c01-9c98-4fda-b123-3f35bcab8fc6")
+	)
+	(segment
+		(start 137.35 105.5)
+		(end 137.65 105.8)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "65e3233a-b642-460e-a68a-0061e04dbd21")
+	)
+	(segment
+		(start 141.9 107.4)
+		(end 142 107.3)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "7083ba98-6af6-49fa-9d9b-e8e586e70a4f")
+	)
+	(segment
+		(start 140.95 88.965255)
+		(end 136.825 84.840255)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "72b4cbb2-270b-4dba-a8f2-9035c9be5946")
+	)
+	(segment
+		(start 140.95 90.7)
+		(end 140.95 88.965255)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "744df1f1-4804-400b-b298-cc600628305f")
+	)
+	(segment
+		(start 138.65 107.4)
+		(end 141.9 107.4)
+		(width 0.2)
+		(layer "F.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "864f962f-a328-4888-a021-4b04abbe7d55")
+	)
+	(via
+		(at 140.95 90.7)
+		(size 0.6)
+		(drill 0.3)
+		(layers "F.Cu" "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "01e75d0e-132e-4c32-a7ed-7e79123a0c57")
+	)
+	(via
+		(at 138.485 72.539999)
+		(size 0.6)
+		(drill 0.3)
+		(layers "F.Cu" "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "034ec525-4d56-4b3b-91b8-82fff126752d")
+	)
+	(via
+		(at 142 107.3)
+		(size 0.6)
+		(drill 0.3)
+		(layers "F.Cu" "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "54dfdcc4-7e5a-46db-a25d-9b3f49cfd01b")
+	)
+	(segment
+		(start 142.7 97.6)
+		(end 142.7 93.5)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "09fe6f92-9e04-4ba4-9d03-c073381dc901")
+	)
+	(segment
+		(start 143.2 98.1)
+		(end 142.7 97.6)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "3f31b1e1-abb7-4e71-b528-b60fbe25a48b")
+	)
+	(segment
+		(start 142 107.3)
+		(end 143.2 106.1)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "41733a2e-2396-4c5b-9393-66bf3739c162")
+	)
+	(segment
+		(start 138.385 72.44)
+		(end 138.485 72.539999)
+		(width 0.3)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "59dd0f51-8058-4c5b-bda6-638a82a844c7")
+	)
+	(segment
+		(start 143.2 106.1)
+		(end 143.2 98.1)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "6b699eb9-7b8d-4f12-abba-c838def9d377")
+	)
+	(segment
+		(start 136.935 72.44)
+		(end 138.385 72.44)
+		(width 0.3)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "89103954-78e1-436f-92b5-11159941f3b9")
+	)
+	(segment
+		(start 140.95 91.75)
+		(end 140.95 90.7)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "b6b0213f-7930-422d-abcf-9df4dbf4a136")
+	)
+	(segment
+		(start 142.7 93.5)
+		(end 140.95 91.75)
+		(width 0.2)
+		(layer "B.Cu")
+		(net "/MCU_Core/PWR_HOLD")
+		(uuid "c221372f-870c-4836-90f0-577b1e33d84b")
+	)
 	(segment
 		(start 131.4 93.051471)
 		(end 133.948529 93.051471)
@@ -35334,190 +35502,6 @@
 		(net "/XBee/XBEE_ON_SLEEP")
 		(uuid "d7d1562f-bb55-429b-b8ed-46044ca26d28")
 	)
-	(segment
-		(start 138.485 74.588529)
-		(end 138.485 72.539999)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "1db3e63b-d7d3-4271-a9fa-b0796ffa017e")
-	)
-	(segment
-		(start 141.4 113.951471)
-		(end 141.751471 113.6)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "2097ce7d-5890-475c-b829-c5e9a6ea50bc")
-	)
-	(segment
-		(start 136.825 76.248529)
-		(end 138.485 74.588529)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "348f6de3-76c0-42e3-a994-073f34529097")
-	)
-	(segment
-		(start 136.5 119.5)
-		(end 136.5 118.75)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "5d9de34d-1e93-4f9b-bd01-4838a795801e")
-	)
-	(segment
-		(start 138.45 118.75)
-		(end 141.4 115.8)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "60dea54a-6440-4d9d-9617-7680300b9486")
-	)
-	(segment
-		(start 136.825 84.840255)
-		(end 136.825 76.248529)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "61817c01-9c98-4fda-b123-3f35bcab8fc6")
-	)
-	(segment
-		(start 140.95 88.965255)
-		(end 136.825 84.840255)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "72b4cbb2-270b-4dba-a8f2-9035c9be5946")
-	)
-	(segment
-		(start 140.95 90.7)
-		(end 140.95 88.965255)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "744df1f1-4804-400b-b298-cc600628305f")
-	)
-	(segment
-		(start 142 113.6)
-		(end 142 107.3)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "7e18483a-dca1-448a-9ddf-87bd9dc36dab")
-	)
-	(segment
-		(start 141.4 115.8)
-		(end 141.4 113.951471)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "829e3cc7-19c8-4b27-92d1-33fc68d49395")
-	)
-	(segment
-		(start 141.751471 113.6)
-		(end 142 113.6)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "b1ee0c93-5f6a-4536-a22f-738e81e468a3")
-	)
-	(segment
-		(start 136.5 118.75)
-		(end 138.45 118.75)
-		(width 0.2)
-		(layer "F.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "ceeac6c4-5ed4-4670-8da9-df820a8633bd")
-	)
-	(via
-		(at 140.95 90.7)
-		(size 0.6)
-		(drill 0.3)
-		(layers "F.Cu" "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "01e75d0e-132e-4c32-a7ed-7e79123a0c57")
-	)
-	(via
-		(at 138.485 72.539999)
-		(size 0.6)
-		(drill 0.3)
-		(layers "F.Cu" "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "034ec525-4d56-4b3b-91b8-82fff126752d")
-	)
-	(via
-		(at 142 107.3)
-		(size 0.6)
-		(drill 0.3)
-		(layers "F.Cu" "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "54dfdcc4-7e5a-46db-a25d-9b3f49cfd01b")
-	)
-	(segment
-		(start 142.7 97.6)
-		(end 142.7 93.5)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "09fe6f92-9e04-4ba4-9d03-c073381dc901")
-	)
-	(segment
-		(start 143.2 98.1)
-		(end 142.7 97.6)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "3f31b1e1-abb7-4e71-b528-b60fbe25a48b")
-	)
-	(segment
-		(start 142 107.3)
-		(end 143.2 106.1)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "41733a2e-2396-4c5b-9393-66bf3739c162")
-	)
-	(segment
-		(start 138.385 72.44)
-		(end 138.485 72.539999)
-		(width 0.3)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "59dd0f51-8058-4c5b-bda6-638a82a844c7")
-	)
-	(segment
-		(start 143.2 106.1)
-		(end 143.2 98.1)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "6b699eb9-7b8d-4f12-abba-c838def9d377")
-	)
-	(segment
-		(start 136.935 72.44)
-		(end 138.385 72.44)
-		(width 0.3)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "89103954-78e1-436f-92b5-11159941f3b9")
-	)
-	(segment
-		(start 140.95 91.75)
-		(end 140.95 90.7)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "b6b0213f-7930-422d-abcf-9df4dbf4a136")
-	)
-	(segment
-		(start 142.7 93.5)
-		(end 140.95 91.75)
-		(width 0.2)
-		(layer "B.Cu")
-		(net "/MCU_Core/PWR_HOLD")
-		(uuid "c221372f-870c-4836-90f0-577b1e33d84b")
-	)
 	(segment
 		(start 138.2 119.5)
 		(end 138.2 120.55)
diff --git a/PCB/v2.x/stackup/board.kdl b/PCB/v2.x/stackup/board.kdl
index 1e7d71f..2fce95d 100644
--- a/PCB/v2.x/stackup/board.kdl
+++ b/PCB/v2.x/stackup/board.kdl
@@ -93,9 +93,10 @@ design snips_controller {
     // Reflows on the last pass, on top: Espressif requires a single reflow for the module. The MINI-1U fits the
     // 17.5 mm between the macro row and the USB pads, where the 19.2 mm WROOM-1U does not.
     // Turned 270 degrees so the signal pins face the stick, the OLED and the carrier, and the GND edge faces the side.
-    // Pins are assigned by position, not from V1's map. PWR_HOLD is on IO42, which has no reset pull (ESP32-S3
+    // Pins are assigned by position, not from V1's map. PWR_HOLD is on IO3, which has no reset pull (ESP32-S3
     // datasheet Table 2-1): RXD0's pull-up could re-latch the board as the rail collapses at power-off. C_LATCH_G1
-    // carries the latch through a short reset, and firmware holds the pin with gpio_hold_en for USB uploads.
+    // carries the latch through a short reset, and firmware holds the pin with gpio_hold_en for USB uploads. It has
+    // to be an RTC pad: on V1 hardware IO3 held through a full upload, and IO42, a digital pad, lost its hold.
     place esp32-s3-mini-1u "U_MCU1" designator="U_MCU1" footprint="Espressif:ESP32-S3-MINI-1U" value="ESP32-S3-MINI-1U-N8" bom_value="Wi-Fi BLE module 8MB flash no PSRAM | ESP32-S3-MINI-1U-N8 | Espressif | SMD module 15.4x15.4mm | N8 variant with external antenna connector"
     // Optional XBee 3 daughter board, hand-soldered to these pads by its castellations. It carries the XBee's
     // decoupling, the RESET pull-up and RC, and the ATTN/BOOTMODE pull-up, so nothing here depends on it being fitted.
@@ -133,7 +134,7 @@ design snips_controller {
     circuit "J_STICK1.p_a" "U_MCU1.IO17" name="/MCU_Core/BTN_STICK"
     circuit "R_BOOT_PU1.A" "SW_BOOT1.2" "U_MCU1.IO0" name="/MCU_Core/MCU_BOOT"
     circuit "C_DBNC1.A" "D_INV_ISO1.K" "R_BTN_PU1.B" "SW_PWR1.1" "U_MCU1.IO21" name="/MCU_Core/PWR_BTN_SENSE"
-    circuit "D_OR2.A" "U_MCU1.IO42" name="/MCU_Core/PWR_HOLD"
+    circuit "D_OR2.A" "U_MCU1.IO3" name="/MCU_Core/PWR_HOLD"
     circuit "R_RGB1.B" "U_MCU1.IO48" name="/MCU_Core/RGB_DIN"
     circuit "R_STAT1.A" "U_CHG1.STAT1" "U_MCU1.IO15" name="/MCU_Core/STAT1"
     circuit "R_STAT2.A" "U_CHG1.STAT2" "U_MCU1.IO14" name="/MCU_Core/STAT2"
@@ -173,7 +174,7 @@ design snips_controller {
     nc "J_USB1.SBU1"
     nc "J_USB1.SBU2"
     nc "U_IMU1.INT2"
-    nc "U_MCU1.IO3" // strap: floating is fine, and a load could upset the JTAG source select
+    nc "U_MCU1.IO42" // no reset pull and free since PWR_HOLD left it: a digital-pad hold does not survive an upload
     nc "U_MCU1.IO45" // strap: stays on its internal pull-down, since high would select 1.8 V flash
     nc "U_MCU1.IO46" // strap: stays on its internal pull-down, so no load can disturb the boot mode
     nc "U_MCU1.TXD0" // prints the boot log, so it stays free for debugging
diff --git a/scripts/spice/README.md b/scripts/spice/README.md
index 5382cc1..a2070e0 100644
--- a/scripts/spice/README.md
+++ b/scripts/spice/README.md
@@ -26,7 +26,7 @@ Set `NGSPICE_LIB` to use a different copy. No Python packages are needed.
 
 ## V2
 
-`latch_v2_sim.py` covers the V2 latch, which differs from V1: PWR_HOLD is on IO42 with no reset pull, C_LATCH_G1 is 1 uF, and R_INV_BASE1 and R_INV_PU1 are 220k. It asserts battery insertion, USB hot-plug with the board off, press time, power-off, riding through a reset (500 ms at 1 uF, 300 ms at an estimated 0.55 uF after bias and tolerance), insertion with the pad ESD diodes into the dead rail, the off drain from the resistors, and a 500 ms press surviving until firmware drives PWR_HOLD 350 ms after the rail comes up. That 350 ms is an estimate until measured. Run it with `python3 scripts/spice/latch_v2_sim.py`. It uses a behavioural buck, and `gpio_hold_en` is firmware, so it is not modeled.
+`latch_v2_sim.py` covers the V2 latch, which differs from V1: PWR_HOLD is on IO3 with no reset pull, C_LATCH_G1 is 1 uF, and R_INV_BASE1 and R_INV_PU1 are 220k. It asserts battery insertion, USB hot-plug with the board off, press time, power-off, riding through a reset (500 ms at 1 uF, 300 ms at an estimated 0.55 uF after bias and tolerance), insertion with the pad ESD diodes into the dead rail, the off drain from the resistors, and a 500 ms press surviving until firmware drives PWR_HOLD 350 ms after the rail comes up. That 350 ms is an estimate until measured. Run it with `python3 scripts/spice/latch_v2_sim.py`. It uses a behavioural buck, and `gpio_hold_en` is firmware, so it is not modeled.
 
 ## Keeping it in sync
 
diff --git a/scripts/spice/latch_v2_sim.py b/scripts/spice/latch_v2_sim.py
index 709596b..881691a 100755
--- a/scripts/spice/latch_v2_sim.py
+++ b/scripts/spice/latch_v2_sim.py
@@ -1,7 +1,7 @@
 #!/usr/bin/env python3
 """ngspice check of the V2 soft latch, which differs from V1 in three ways.
 
-PWR_HOLD is on IO42, which has no reset pull, so the pin floats during a reset. C_LATCH_G1 is 1 uF so
+PWR_HOLD is on IO3, which has no reset pull, so the pin floats during a reset. C_LATCH_G1 is 1 uF so
 the latch rides through a short reset, and R_INV_BASE1 and R_INV_PU1 are 220k to cut the off current.
 
   insert    battery plugged in with the board off: the gate stays low
@@ -80,7 +80,7 @@ def dead_rail():
 
 
 def clamped_rail(crail):
-    """The dead rail with the ESD diodes of IO21, IO42 and IO10 into it, and the VSYS divider on IO10."""
+    """The dead rail with the ESD diodes of IO21, IO3 and IO10 into it, and the VSYS divider on IO10."""
     return (f"Rv1 vsys io10 200k\nRv2 io10 0 100k\nCv io10 0 100n\nDio10 io10 v3v3 DESD\nDio21 sense v3v3 DESD\n"
             f"Dio42 hold v3v3 DESD\n.model DESD D(IS=1e-14 N=1.05)\nR3 v3v3 0 311k\nC3 v3v3 0 {crail}\nRh hold 0 100Meg\n")