From e2d59ed1d60655f2d341544277d96282eeeef1fd Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Mon, 10 Aug 2026 19:27:32 +0800 Subject: [PATCH 1/2] FROMLIST: dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Add vdda-refgen and refgen supply properties QCS8300 and SA8775p PCIe PHYs require dedicated vdda-refgen and refgen LDO supplies for QREF to provide a stable reference clock. Without these supplies, the PCIe PHYs cannot work properly. Mark them as required for the affected compatibles even though it breaks ABI. vdda-refgen-supply is required for all three QCS8300 and SA8775p PHY compatibles. refgen-supply is required for QCS8300 only, as a workaround for a hardware issue where QREF actually depends on refgen3 rather than refgen2 as documented, so the PHY driver votes for refgen3 directly via this supply. Link: https://lore.kernel.org/all/20260810112735.1326807-2-ziyue.zhang@oss.qualcomm.com/ Signed-off-by: Ziyue Zhang Reviewed-by: Krzysztof Kozlowski Signed-off-by: Qiang Yu --- .../phy/qcom,sc8280xp-qmp-pcie-phy.yaml | 27 +++++++++++++++++++ 1 file changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index 375f5fb2111fd..a5feedaa2c44f 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -95,6 +95,11 @@ properties: vdda-refgen1p2-supply: true + vdda-refgen-supply: true + + # Only required on platforms where the hardware voting doesn't work properly + refgen-supply: true + qcom,4ln-config-sel: description: PCIe 4-lane configuration $ref: /schemas/types.yaml#/definitions/phandle-array @@ -277,6 +282,28 @@ allOf: - vdda-refgen0p9-supply - vdda-refgen1p2-supply + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy + then: + required: + - vdda-refgen-supply + + - if: + properties: + compatible: + contains: + enum: + - qcom,qcs8300-qmp-gen4x2-pcie-phy + then: + required: + - refgen-supply + examples: - | #include From 5e959ea7e42fc5a8a5241b98d1b3a246c06a36ad Mon Sep 17 00:00:00 2001 From: Ziyue Zhang Date: Mon, 10 Aug 2026 19:27:33 +0800 Subject: [PATCH 2/2] FROMLIST: phy: qcom: qmp-pcie: Add qref and refgen regulator vote for QCS8300 and SA8775p PHY Add a new sa8775p_qmp_phy_vreg_l that includes vdda-phy, vdda-pll, vdda-qref, vdda-refgen and refgen supplies, and use it for QCS8300 and SA8775p PCIe PHY configurations. This avoids modifying sm8550_qmp_phy_vreg_l and breaking SM8550 and SM8650. Note that due to a hardware issue, QREF actually depends on refgen3 rather than refgen2 as documented; refgen3 is therefore voted manually via the refgen supply as a workaround. Link: https://lore.kernel.org/all/20260810112735.1326807-3-ziyue.zhang@oss.qualcomm.com/ Fixes: a05b6d5135ec ("phy: qcom-qmp-pcie: add support for sa8775p") Fixes: ebf198f17b5a ("phy: qcom-qmp-pcie: add dual lane PHY support for QCS8300") Signed-off-by: Ziyue Zhang Signed-off-by: Qiang Yu --- drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c index 30971c8402dae..c0e1ca3c01add 100644 --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c @@ -3484,6 +3484,10 @@ static const char * const qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", }; +static const char * const sa8775p_qmp_phy_vreg_l[] = { + "vdda-phy", "vdda-pll", "vdda-qref", "vdda-refgen", "refgen", +}; + static const char * const sm8550_qmp_phy_vreg_l[] = { "vdda-phy", "vdda-pll", "vdda-qref", }; @@ -4398,8 +4402,8 @@ static const struct qmp_phy_cfg sm8450_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sa8775p_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4567,8 +4571,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x2_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sa8775p_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL, @@ -4608,8 +4612,8 @@ static const struct qmp_phy_cfg sa8775p_qmp_gen4x4_pciephy_cfg = { .reset_list = sdm845_pciephy_reset_l, .num_resets = ARRAY_SIZE(sdm845_pciephy_reset_l), - .vreg_list = qmp_phy_vreg_l, - .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), + .vreg_list = sa8775p_qmp_phy_vreg_l, + .num_vregs = ARRAY_SIZE(sa8775p_qmp_phy_vreg_l), .regs = pciephy_v5_regs_layout, .pwrdn_ctrl = SW_PWRDN | REFCLK_DRV_DSBL,