diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml
new file mode 100644
index 00000000..07c88da3
--- /dev/null
+++ b/.github/workflows/gitlab-ci.yml
@@ -0,0 +1,16 @@
+name: gitlab-ci
+
+on: [ push, pull_request, workflow_dispatch ]
+
+jobs:
+  gitlab-ci:
+    runs-on: ubuntu-latest
+    steps:
+      - name: Check Gitlab CI
+        uses: pulp-platform/pulp-actions/gitlab-ci@v2.5.1 # update version as needed, not autoupdated
+        # Skip on forks or pull requests from forks due to missing secrets.
+        if: github.repository == 'FondazioneChipsIT/pulp' && (github.event_name != 'pull_request' || github.event.pull_request.head.repo.full_name == github.repository)
+        with:
+         domain: gitlab.chips.it
+         repo: digitalresearchline/githubmirrors/pulp
+         token: ${{ secrets.GITLAB_TOKEN }}
\ No newline at end of file
diff --git a/.gitignore b/.gitignore
index 6844b923..da20b75d 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,6 +8,7 @@
 /tests/*/
 /pulp-runtime
 /regression_tests
+nonfree
 
 # Bender
 /bender
@@ -16,3 +17,41 @@
 /sim/transcript
 /sim/work
 /working_dir
+
+# logs
+*.log
+*.db
+*.bin
+.qsim
+sim/**/*.txt
+
+# External SDKs / tools checked out locally
+/Deeploy/
+/gvsoc/
+/pulp-sdk/
+
+# Simulation outputs
+/sim/stdout/
+/sim/vectors/
+/sim/*.vstf
+
+# Waveform / EDA artifacts
+*.vcd
+*.fst
+*.wdb
+*.jou
+*.str
+
+# Python
+*.pyc
+*.egg-info/
+
+# Editor / OS
+.DS_Store
+*.swp
+*~
+
+# other tools
+.vscode
+.claude
+
diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 280b5649..10098e92 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -12,209 +12,37 @@
 # See the License for the specific language governing permissions and
 # limitations under the License.
 
-
-variables:
-  PATH: "/home/gitlabci/bin:/usr/lib64/qt-3.3/bin:/bin:/usr/bin:/usr/local/bin:/sbin:/usr/sbin:/usr/local/sbin:/usr/local/condor/bin:/usr/sepp/bin:/usr/local/anaconda3/bin:/var/lib/snapd/snap/bin"
-before_script:
-  - pwd
-  - echo "$PATH"
-
-# after_script:
-#   - echo "stage finished"
-
 stages:
-  - fetch
-  - build_and_test_boot
-  - build_and_test
-  - build_and_test_vips
-  - build_and_test_psram
-  - build_fpga
-  - sim_questa_multivers
-
-
-fetch_std:
-  stage: fetch
-  script:
-    - echo "Fetching regression tests"
-    - make test-checkout-gitlab
-    - mkdir -p regression_tests/riscv_tests_soc
-    - cp -r regression_tests/riscv_tests/* regression_tests/riscv_tests_soc
-    - mkdir regression_tests/hellospi
-    - cp -r regression_tests/hello/* regression_tests/hellospi/
-    - mkdir regression_tests/hellohyper
-    - cp -r regression_tests/hello/* regression_tests/hellohyper/
-    - source setup/vsim.sh
-    - echo "Fetching IPs"
-    - make checkout
-    - echo "Fetching vips"
-    - ./rtl/vip/get-vips.sh --yes --gitlab
-  artifacts:
-    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
-    paths:
-      - .bender/*
-      - bender
-      - Bender.lock
-      - sim/*
-      - rtl/vip/*
-      - regression_tests/*
-
-b&t_rtl_std:
-  stage: build_and_test
-  before_script:
-    - echo "Generate scripts without DPI and VIP support"
-    - make scripts
-    - echo "Compiling RTL model and DPI libraries"
-    - make build
-    - echo "Fetching Runtime"
-    - make pulp-runtime
-    - echo "Source and exports"
-    - source pulp-runtime/configs/pulp.sh; 
-    - export PULP_RISCV_GCC_TOOLCHAIN=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/
-    - export PATH=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/bin/:$PATH
-  script:
-    - echo "Running software test"
-    - make test-fast-regressions
-  artifacts:
-    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
-    paths:
-      - .bender/*
-      - bender
-      - Bender.lock
-      - regression_tests/*
-      - tests/*
-      - sim/*
-      - rtl/*
-    reports:
-      junit: regression_tests/simplified-runtime.xml
-
+  - nonfree
+  - PULP_CI
 
-b&t_rtl_vip:
-  stage: build_and_test_vips
-  before_script:
-    - echo "Generate scripts with DPI and VIP support"
-    - make scripts-vips
-    - echo "Compiling RTL model and DPI libraries"
-    - make build
-    - echo "Fetching Runtime"
-    - make pulp-runtime
-    - echo "Source and exports"
-    - source pulp-runtime/configs/pulp.sh; 
-    - export PULP_RISCV_GCC_TOOLCHAIN=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/
-    - export PATH=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/bin/:$PATH
-  script:
-    - echo "Running software test"
-    - make git-ci-periphs-regs
+init:
+  stage: nonfree
+  script: make pulp_nonfree_init
   artifacts:
-    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
     paths:
-      - .bender/*
-      - bender
-      - Bender.lock
-      - regression_tests/*
-      - sim/*
-      - rtl/*
-    reports:
-      junit: regression_tests/simplified-periph-runtime.xml
-
-b&t_rtl_boot:
-  stage: build_and_test_boot
-  before_script:
-    - echo "Generate scripts with DPI and VIP support"
-    - make scripts-vips
-    - echo "Compiling RTL model and DPI libraries"
-    - make build
-    - echo "Fetching Runtime"
-    - git clone  https://github.com/pulp-platform/pulp-runtime.git -b boot_code_update
-    - echo "Source and exports"
-    - source pulp-runtime/configs/pulp.sh; 
-    - export PULP_RISCV_GCC_TOOLCHAIN=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/
-    - export PATH=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/bin/:$PATH
-  script:
-    - echo "Running software test"
-    - make git-boot
-  artifacts:
-    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
-    paths:
-      - .bender/*
-      - bender
-      - Bender.lock
-      - regression_tests/*
-      - sim/*
-      - rtl/*
-    reports:
-      junit: regression_tests/boot-runtime.xml
-
-
-b&t_rtl_psram:
-  stage: build_and_test_psram
-  before_script:
-    - echo "Generate scripts with DPI and VIP support"
-    - make scripts-psram
-    - echo "Compiling RTL model and DPI libraries"
-    - make build
-    - echo "Fetching Runtime"
-    - make pulp-runtime
-    - echo "Source and exports"
-    - source pulp-runtime/configs/pulp.sh; 
-    - export PULP_RISCV_GCC_TOOLCHAIN=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/
-    - export PATH=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/bin/:$PATH
-  script:
-    - echo "Running software test"
-    - make git-ci-psram
-  artifacts:
-    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
-    paths:
-      - .bender/*
-      - bender
-      - Bender.lock
-      - regression_tests/*
-      - sim/*
-      - rtl/*
-    reports:
-      junit: regression_tests/simplified-psram-runtime.xml
-
-build_fpga:
-  stage: build_fpga
-  before_script:
-    - echo "Generate scripts for FPGA"
-    - make scripts
-  script:
-    - echo "Building for zcu102"
-    - make -C fpga zcu102 VIVADO='vivado-2019.1.1 vivado'
-  artifacts:
-    name: "$CI_JOB_NAME-$CI_COMMIT_REF_NAME-$CI_COMMIT_SHORT_SHA"
-    paths:
-      - fpga/*
-
-sim_questa_multivers:
-  stage: sim_questa_multivers
-  allow_failure: true
-  when: always
-  parallel:
-    matrix:
-      - QUESTA_PREFIX:
-        - 'questa-2019.3'
-        - 'questa-2020.1'
-        - 'questa-2021.3'
-  before_script:
-    - export VSIM="$QUESTA_PREFIX vsim"
-    - export VLOG="$QUESTA_PREFIX vlog"
-    - export VOPT="$QUESTA_PREFIX vopt"
-    - export VLIB="$QUESTA_PREFIX vlib"
-    - export VMAP="$QUESTA_PREFIX vmap"
-    - export VCOM="$QUESTA_PREFIX vcom"
-    - export PULP_RISCV_GCC_TOOLCHAIN=/usr/pack/pulpsdk-1.0-kgf/artifactory/pulp-sdk-release/pkg/pulp_riscv_gcc/1.0.16/
-    - git clone https://github.com/pulp-platform/pulp-runtime.git -b v0.0.15
-    - mkdir hello
-    - printf "#include <stdio.h>\nint main(){\n  printf(\"Hello World\\\n\");\n  return 0;\n}\n" > hello/hello.c
-    - printf "PULP_APP = hello\nPULP_APP_FC_SRCS = hello.c\nPULP_APP_HOST_SRCS = hello.c\nPULP_CFLAGS = -O3 -g\n\ninclude \$(PULP_SDK_HOME)/install/rules/pulp_rt.mk\n" > hello/Makefile
-  script:
-    - make scripts
-    - make clean build
-    - source setup/vsim.sh
-    - source pulp-runtime/configs/pulp.sh
-    - make -C hello clean all run
-  dependencies:
-    - fetch_std
-  needs:
-    - fetch_std
+      - nonfree/.gitlab-ci.yml
+      - nonfree/.gitlab-ci_fpga.yml
+
+subpipe_rtl:
+  stage: PULP_CI
+  needs: [ init ]
+  variables:
+    PARENT_PIPELINE_SOURCE: $CI_PIPELINE_SOURCE
+  trigger:
+    include:
+      - artifact: nonfree/.gitlab-ci.yml
+        job: init
+    strategy: depend
+
+subpipe_fpga:
+  stage: PULP_CI
+  needs: [ init ]
+  when: manual
+  variables:
+    PARENT_PIPELINE_SOURCE: $CI_PIPELINE_SOURCE
+  trigger:
+    include:
+      - artifact: nonfree/.gitlab-ci_fpga.yml
+        job: init
+    strategy: depend
diff --git a/Bender.lock b/Bender.lock
index c942e0ed..420efeee 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -1,440 +1,541 @@
----
 packages:
   adv_dbg_if:
-    revision: 19eeef8cae1cbec7413877b3f29fe0bd078748d7
+    revision: c4d7aa177ef96b0fdff8748f81bd15489446c95a
     version: 0.0.2
     source:
-      Git: "https://github.com/pulp-platform/adv_dbg_if.git"
+      Git: https://github.com/pulp-platform/adv_dbg_if.git
     dependencies: []
   apb:
     revision: d077333a7e5cc80008935dc2761440532dfdce81
     version: 0.1.0
     source:
-      Git: "https://github.com/pulp-platform/apb.git"
+      Git: https://github.com/pulp-platform/apb.git
     dependencies: []
   apb2per:
     revision: 6fc13fc0bfa71772d91391893e57306d0d95befa
     version: 0.1.0
     source:
-      Git: "https://github.com/pulp-platform/apb2per.git"
+      Git: https://github.com/pulp-platform/apb2per.git
     dependencies: []
   apb_adv_timer:
     revision: c8faec1e1755386d0e0f31a55ebd80612a3dcea9
     version: 1.0.4
     source:
-      Git: "https://github.com/pulp-platform/apb_adv_timer.git"
+      Git: https://github.com/pulp-platform/apb_adv_timer.git
     dependencies:
-      - tech_cells_generic
+    - tech_cells_generic
   apb_fll_if:
     revision: a1f67b624fe379d4d319c809656b672f0267cfc8
     version: 0.1.3
     source:
-      Git: "https://github.com/pulp-platform/apb_fll_if.git"
+      Git: https://github.com/pulp-platform/apb_fll_if.git
     dependencies:
-      - apb
+    - apb
   apb_gpio:
     revision: 0e9f142f2f11278445c953ad011fce1c7ed85b66
-    version: ~
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/apb_gpio.git"
+      Git: https://github.com/pulp-platform/apb_gpio.git
     dependencies: []
   apb_interrupt_cntrl:
     revision: 86d650f590a385cc0d5148125528527377f0527c
     version: 0.1.2
     source:
-      Git: "https://github.com/pulp-platform/apb_interrupt_cntrl.git"
+      Git: https://github.com/pulp-platform/apb_interrupt_cntrl.git
     dependencies:
-      - common_cells
+    - common_cells
   apb_node:
     revision: 4e350ef4980141397e3e17ced00e310e30f8dc95
     version: 0.1.1
     source:
-      Git: "https://github.com/pulp-platform/apb_node.git"
+      Git: https://github.com/pulp-platform/apb_node.git
     dependencies:
-      - apb
+    - apb
   axi:
-    revision: 527cf64a95f7aea36836b2db76dc4d767e150358
-    version: 0.29.2
+    revision: 78831b6feba265d5ee2683bbf42b4150f8a35c43
+    version: 0.39.8
     source:
-      Git: "https://github.com/pulp-platform/axi.git"
+      Git: https://github.com/pulp-platform/axi.git
     dependencies:
-      - common_cells
-      - common_verification
+    - common_cells
+    - common_verification
+    - tech_cells_generic
   axi2mem:
-    revision: 6973e0434d26ba578cdb4aa69c26c1facd1a3f15
-    version: ~
+    revision: be0c696709acaee579787ba2432d26ad27640594
+    version: 1.0.2
     source:
-      Git: "https://github.com/pulp-platform/axi2mem.git"
+      Git: https://github.com/pulp-platform/axi2mem.git
     dependencies:
-      - axi_slice
-      - common_cells
+    - axi_slice
+    - common_cells
   axi2per:
-    revision: a99ef2fac9f3b087671109a27c766f25e8e0f115
-    version: 1.0.1
+    revision: e8ca052a745e184ca960933b2fe416b725e9ca81
+    version: 1.0.2
     source:
-      Git: "https://github.com/pulp-platform/axi2per.git"
+      Git: https://github.com/pulp-platform/axi2per.git
     dependencies:
-      - axi_slice
+    - axi_slice
   axi_slice:
     revision: a4f72bc21ac4d7da631e8309d9f8d0c34b735c23
     version: 1.1.4
     source:
-      Git: "https://github.com/pulp-platform/axi_slice.git"
+      Git: https://github.com/pulp-platform/axi_slice.git
     dependencies:
-      - common_cells
+    - common_cells
+  axi_stream:
+    revision: 54891ff40455ca94a37641b9da4604647878cc07
+    version: 0.1.1
+    source:
+      Git: https://github.com/pulp-platform/axi_stream.git
+    dependencies:
+    - common_cells
+  cluster_icache:
+    revision: 64e21ae455bbdde850c4df13bef86ea55ac42537
+    version: 0.2.0
+    source:
+      Git: https://github.com/pulp-platform/cluster_icache.git
+    dependencies:
+    - axi
+    - common_cells
+    - register_interface
+    - scm
+    - tech_cells_generic
   cluster_interconnect:
-    revision: 7d0a4f8acae71a583a6713cab5554e60b9bb8d27
-    version: 1.2.1
+    revision: 2967d8d17be0a6139229ca8d3d4956e182aec3de
+    version: 1.3.0
     source:
-      Git: "https://github.com/pulp-platform/cluster_interconnect.git"
+      Git: https://github.com/pulp-platform/cluster_interconnect.git
     dependencies:
-      - common_cells
+    - common_cells
   cluster_peripherals:
-    revision: d388a790d9e1129e3ec57b2e0075ee21e454c3b1
-    version: 2.1.0
+    revision: 71c17eea6e5dbc26a8d07290d4bbfe0670f7edfe
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/cluster_peripherals.git"
+      Git: https://github.com/pulp-platform/cluster_peripherals.git
     dependencies:
-      - hci
+    - hci
   common_cells:
-    revision: b5ec8905ed7828655155b0ae971023adf793c600
-    version: 1.24.0
+    revision: 9afda9abb565971649c2aa0985639c096f351171
+    version: 1.38.0
     source:
-      Git: "https://github.com/pulp-platform/common_cells.git"
+      Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
-      - common_verification
-      - tech_cells_generic
+    - common_verification
+    - tech_cells_generic
   common_verification:
-    revision: b616c1a25aea3b76e32dcbed2ec87d057efdcffd
-    version: 0.2.1
+    revision: fb1885f48ea46164a10568aeff51884389f67ae3
+    version: 0.2.5
     source:
-      Git: "https://github.com/pulp-platform/common_verification.git"
+      Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cv32e40p:
-    revision: 8d58109ab61e1fb6c9dcbafefb8f3a56ee596427
-    version: ~
+    revision: 1a93f340e9dadb9f7c8c471f27a40932c8b1c62e
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/cv32e40p.git"
+      Git: https://github.com/pulp-platform/cv32e40p.git
     dependencies:
-      - fpnew
-      - tech_cells_generic
+    - common_cells
+    - fpnew
+    - tech_cells_generic
+  cv32e40x:
+    revision: 96b933ac2f723351872da55e7d2e9a82abd5df34
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/cv32e40x.git
+    dependencies: []
   event_unit_flex:
-    revision: 53fb3a1093aaaedfe883739fd8a3155d601210bc
-    version: ~
+    revision: 28e0499374117c7b0ef4c6ad81b60d7526af886f
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/event_unit_flex.git"
+      Git: https://github.com/pulp-platform/event_unit_flex.git
     dependencies:
-      - common_cells
+    - common_cells
+  flex-v:
+    revision: e9355c2f6ec4c105abdff39489e5d1be93bc4374
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/flex-v.git
+    dependencies:
+    - fpnew
+    - tech_cells_generic
   fpnew:
-    revision: 8dc44406b1ccbc4487121710c1883e805f893965
-    version: 0.6.6
+    revision: e5aa6a01b5bbe1675c3aa8872e1203413ded83d1
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/fpnew.git"
+      Git: https://github.com/pulp-platform/cvfpu.git
     dependencies:
-      - common_cells
-      - fpu_div_sqrt_mvp
+    - common_cells
+    - fpu_div_sqrt_mvp
   fpu_div_sqrt_mvp:
     revision: 86e1f558b3c95e91577c41b2fc452c86b04e85ac
     version: 1.0.4
     source:
-      Git: "https://github.com/pulp-platform/fpu_div_sqrt_mvp.git"
+      Git: https://github.com/pulp-platform/fpu_div_sqrt_mvp.git
     dependencies:
-      - common_cells
-  fpu_interco:
-    revision: 66b4084117546d5b748c30b5500769805f489d2f
-    version: ~
-    source:
-      Git: "https://github.com/pulp-platform/fpu_interco.git"
-    dependencies:
-      - cv32e40p
-      - fpnew
+    - common_cells
   generic_fll:
     revision: 1c92dc73a940392182fd4cb7b86f35649b349595
-    version: ~
+    version: 0.2.0
     source:
-      Git: "https://github.com/pulp-platform/generic_FLL.git"
+      Git: https://github.com/pulp-platform/generic_FLL.git
     dependencies: []
   hci:
-    revision: 8fb848e8f6722c1c21b44533535f430960c31b0b
-    version: 1.0.8
+    revision: 3e63936991569d0b1e315d6914478937b37bb338
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/hci.git"
+      Git: https://github.com/FondazioneChipsIT/hci.git
     dependencies:
-      - cluster_interconnect
-      - hwpe-stream
-      - l2_tcdm_hybrid_interco
+    - cluster_interconnect
+    - common_cells
+    - hwpe-stream
+    - l2_tcdm_hybrid_interco
+    - redundancy_cells
+    - register_interface
   hier-icache:
-    revision: c82025995fbb18e045bb14ad2e94b35734994956
-    version: ~
+    revision: 7243834d2407ca23cff583d57641c84b982bd9bc
+    version: 1.3.0
     source:
-      Git: "https://github.com/pulp-platform/hier-icache.git"
+      Git: https://github.com/FondazioneChipsIT/hier-icache.git
     dependencies:
-      - axi
-      - axi_slice
-      - common_cells
-      - icache-intc
-      - scm
-      - tech_cells_generic
+    - axi
+    - axi_slice
+    - common_cells
+    - icache-intc
+    - scm
+    - tech_cells_generic
   hwpe-ctrl:
-    revision: 0336a85f7515fbd50ffab1a3290812401ef321b6
-    version: 1.6.2
-    source:
-      Git: "https://github.com/pulp-platform/hwpe-ctrl.git"
-    dependencies:
-      - tech_cells_generic
-  hwpe-datamover-example:
-    revision: 47e7fe8a38331b123d763ecab11be4058d425021
-    version: 1.0.1
+    revision: 3690a3c648f120546d8de2bc583d5170c36d2f20
+    version: 2.0.0
     source:
-      Git: "https://github.com/pulp-platform/hwpe-datamover-example.git"
+      Git: https://github.com/pulp-platform/hwpe-ctrl.git
     dependencies:
-      - hci
-      - hwpe-ctrl
-      - hwpe-stream
+    - tech_cells_generic
   hwpe-mac-engine:
     revision: cd48c574f1972ecbe02d3f463a0e12a92acde484
     version: 1.3.3
     source:
-      Git: "https://github.com/pulp-platform/hwpe-mac-engine.git"
+      Git: https://github.com/pulp-platform/hwpe-mac-engine.git
     dependencies:
-      - hwpe-ctrl
-      - hwpe-stream
+    - hwpe-ctrl
+    - hwpe-stream
   hwpe-stream:
-    revision: ddc154424187dff42a8fcec946c768ceb13f13de
-    version: 1.6.4
+    revision: b3d33afdd27e79bcda1348d0ab5f4afd52c03106
+    version: 1.9.0
     source:
-      Git: "https://github.com/pulp-platform/hwpe-stream.git"
+      Git: https://github.com/pulp-platform/hwpe-stream.git
     dependencies:
-      - tech_cells_generic
+    - tech_cells_generic
   ibex:
-    revision: 95b85ddd1c995ace9f89ee42530f9e24820c1051
-    version: ~
+    revision: b18f7ef178ed07f5085051f96042c670a919fd5c
+    version: null
     source:
-      Git: "https://github.com/lowRISC/ibex.git"
+      Git: https://github.com/pulp-platform/ibex.git
     dependencies:
-      - tech_cells_generic
+    - tech_cells_generic
   icache-intc:
     revision: 663c3b6d3c2bf63ff25cda46f33c799c647b3985
     version: 1.0.1
     source:
-      Git: "https://github.com/pulp-platform/icache-intc.git"
+      Git: https://github.com/pulp-platform/icache-intc.git
     dependencies: []
-  icache_mp_128_pf:
-    revision: 6f2e54102001230db9c82432bf9e011842419a48
-    version: ~
-    source:
-      Git: "https://github.com/pulp-platform/icache_mp_128_pf.git"
-    dependencies:
-      - axi_slice
-      - common_cells
-      - icache-intc
-      - scm
+  idma:
+    revision: 7073edd83950232c12f900d2b6d65016b886a50a
+    version: null
+    source:
+      Git: https://github.com/FondazioneChipsIT/iDMA.git
+    dependencies:
+    - axi
+    - axi_stream
+    - common_cells
+    - common_verification
+    - obi
+    - register_interface
   jtag_pulp:
-    revision: 5ace3495a6d35552e2009e9dece75452ac3cd82b
-    version: 0.1.0
+    revision: d22e828aef0484c79355d97d12de044c97e1f20f
+    version: 0.2.0
     source:
-      Git: "https://github.com/pulp-platform/jtag_pulp.git"
+      Git: https://github.com/pulp-platform/jtag_pulp.git
     dependencies: []
   l2_tcdm_hybrid_interco:
     revision: fa55e72859dcfb117a2788a77352193bef94ff2b
     version: 1.0.0
     source:
-      Git: "https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git"
+      Git: https://github.com/pulp-platform/L2_tcdm_hybrid_interco.git
     dependencies: []
   mchan:
-    revision: a9c71f2d9845a4ca05cf2c6ad089b4753f76fc2e
-    version: 1.2.3
+    revision: 3f2ae92f78e2ddbd0e079cbb4f81fcc248171c12
+    version: 1.2.4
+    source:
+      Git: https://github.com/pulp-platform/mchan.git
+    dependencies:
+    - common_cells
+  neureka:
+    revision: 2e076f7d25cdfba38821ee95595bb27aec53c764
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/mchan.git"
+      Git: https://github.com/pulp-platform/neureka.git
     dependencies:
-      - common_cells
+    - hci
+    - hwpe-ctrl
+    - hwpe-stream
+    - register_interface
+    - zeroriscy
+  obi:
+    revision: 0155fc34e900c7c884e081c0a1114a247937ff69
+    version: 0.1.7
+    source:
+      Git: https://github.com/pulp-platform/obi.git
+    dependencies:
+    - common_cells
+    - common_verification
   per2axi:
-    revision: 892fcad60b6374fe558cbde76f4a529d473ba5ca
-    version: 1.0.4
+    revision: 18cf4f2ad51b73de0448843ce0def54ab5fb274b
+    version: 1.0.5
     source:
-      Git: "https://github.com/pulp-platform/per2axi.git"
+      Git: https://github.com/pulp-platform/per2axi.git
     dependencies:
-      - axi_slice
+    - axi_slice
   pulp_cluster:
-    revision: 040fc3e3b2dbf11ce0d08bf7554f310c483b8c9f
-    version: ~
-    source:
-      Git: "https://github.com/pulp-platform/pulp_cluster.git"
-    dependencies:
-      - axi
-      - axi2mem
-      - axi2per
-      - axi_slice
-      - cluster_interconnect
-      - cluster_peripherals
-      - common_cells
-      - cv32e40p
-      - event_unit_flex
-      - fpu_interco
-      - hci
-      - hier-icache
-      - hwpe-datamover-example
-      - ibex
-      - icache_mp_128_pf
-      - mchan
-      - per2axi
-      - scm
-      - tech_cells_generic
-      - timer_unit
+    revision: 23cf745df8c86b92ae9171e68de85e074e49dc8b
+    version: null
+    source:
+      Git: https://github.com/FondazioneChipsIT/pulp_cluster.git
+    dependencies:
+    - axi
+    - axi2mem
+    - axi2per
+    - cluster_icache
+    - cluster_interconnect
+    - cluster_peripherals
+    - common_cells
+    - cv32e40p
+    - event_unit_flex
+    - flex-v
+    - hci
+    - hier-icache
+    - ibex
+    - idma
+    - mchan
+    - neureka
+    - obi
+    - per2axi
+    - redmule
+    - redundancy_cells
+    - register_interface
+    - scm
+    - softex
+    - tech_cells_generic
+    - timer_unit
   pulp_soc:
-    revision: d878151e0e40912642c5275d470cef76258f5fc6
-    version: 3.0.1
-    source:
-      Git: "https://github.com/pulp-platform/pulp_soc.git"
-    dependencies:
-      - adv_dbg_if
-      - apb
-      - apb2per
-      - apb_adv_timer
-      - apb_fll_if
-      - apb_gpio
-      - apb_interrupt_cntrl
-      - apb_node
-      - axi
-      - axi_slice
-      - cluster_interconnect
-      - common_cells
-      - cv32e40p
-      - fpnew
-      - generic_fll
-      - hwpe-mac-engine
-      - ibex
-      - jtag_pulp
-      - l2_tcdm_hybrid_interco
-      - register_interface
-      - riscv-dbg
-      - scm
-      - tech_cells_generic
-      - timer_unit
-      - udma_camera
-      - udma_core
-      - udma_external_per
-      - udma_filter
-      - udma_hyper
-      - udma_i2c
-      - udma_i2s
-      - udma_qspi
-      - udma_sdio
-      - udma_uart
+    revision: a6967f9d654f1754e0564f9947e3a88409747ab7
+    version: null
+    source:
+      Git: https://github.com/FondazioneChipsIT/pulp_soc.git
+    dependencies:
+    - adv_dbg_if
+    - apb
+    - apb2per
+    - apb_adv_timer
+    - apb_fll_if
+    - apb_gpio
+    - apb_interrupt_cntrl
+    - apb_node
+    - axi
+    - axi_slice
+    - cluster_interconnect
+    - common_cells
+    - fpnew
+    - generic_fll
+    - hwpe-mac-engine
+    - ibex
+    - jtag_pulp
+    - l2_tcdm_hybrid_interco
+    - register_interface
+    - riscv
+    - riscv-dbg
+    - scm
+    - tech_cells_generic
+    - timer_unit
+    - udma_camera
+    - udma_core
+    - udma_external_per
+    - udma_filter
+    - udma_hyper
+    - udma_i2c
+    - udma_i2s
+    - udma_qspi
+    - udma_sdio
+    - udma_uart
+  redmule:
+    revision: dbcba6b1efda24dc909ebdd4ace132f798c8c12b
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/redmule.git
+    dependencies:
+    - common_cells
+    - cv32e40p
+    - cv32e40x
+    - fpnew
+    - hci
+    - hwpe-ctrl
+    - hwpe-stream
+    - ibex
+    - obi
+    - register_interface
+    - tech_cells_generic
+  redundancy_cells:
+    revision: 6ba6f415a9024decedabaf3f2b45263ff546dabd
+    version: null
+    source:
+      Git: https://github.com/pulp-platform/redundancy_cells.git
+    dependencies:
+    - common_cells
+    - common_verification
+    - register_interface
+    - tech_cells_generic
   register_interface:
-    revision: 73de8e51b79f416350229b1d2420b2c527e002b8
-    version: 0.3.1
+    revision: d6e1d4cdaab7870f4faf3f88a1c788eaf5ac129d
+    version: 0.4.6
+    source:
+      Git: https://github.com/pulp-platform/register_interface.git
+    dependencies:
+    - apb
+    - axi
+    - common_cells
+    - common_verification
+  riscv:
+    revision: c760db14dbd6cc3ec3b8ae8274df2eac7225bcac
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/register_interface.git"
+      Git: https://github.com/AlSaqr-platform/riscv_nn.git
     dependencies:
-      - axi
-      - common_cells
+    - fpnew
+    - tech_cells_generic
   riscv-dbg:
     revision: e19d69efe7d7e4da6c25ed91d5e7f501ab52dd68
     version: 0.4.1
     source:
-      Git: "https://github.com/pulp-platform/riscv-dbg.git"
+      Git: https://github.com/pulp-platform/riscv-dbg.git
     dependencies: []
   scm:
-    revision: e1ad7dffd9d8702430131ec8bc1a0d9ff686ece2
-    version: 1.1.0
+    revision: 472f99affe44ff7b282b519c047a3cfeb35b16c6
+    version: 1.2.0
     source:
-      Git: "https://github.com/pulp-platform/scm.git"
-    dependencies: []
+      Git: https://github.com/pulp-platform/scm.git
+    dependencies:
+    - tech_cells_generic
+  softex:
+    revision: 11dd29e85d40e29fea0481b471f1c0cc967df1a4
+    version: null
+    source:
+      Git: https://github.com/belanoa/softex.git
+    dependencies:
+    - common_cells
+    - fpnew
+    - hci
+    - hwpe-ctrl
+    - hwpe-stream
+    - ibex
   tbtools:
     revision: 4bc2c825df8540a0c0210ab7f484533809801fa2
     version: 0.2.1
     source:
-      Git: "https://github.com/pulp-platform/tbtools.git"
+      Git: https://github.com/pulp-platform/tbtools.git
     dependencies: []
   tech_cells_generic:
-    revision: e6226a6f374eb88fed84d4989bb3f066cb470f33
-    version: 0.2.9
+    revision: 7968dd6e6180df2c644636bc6d2908a49f2190cf
+    version: 0.2.13
     source:
-      Git: "https://github.com/pulp-platform/tech_cells_generic.git"
+      Git: https://github.com/pulp-platform/tech_cells_generic.git
     dependencies:
-      - common_verification
+    - common_verification
   timer_unit:
-    revision: 3f4ee3e5b3875a473242de5d0c3ebb5a0fe4b8db
-    version: 1.0.2
+    revision: 4c69615c89db9397a9747d6f6d6a36727854f0bc
+    version: 1.0.3
     source:
-      Git: "https://github.com/pulp-platform/timer_unit.git"
+      Git: https://github.com/pulp-platform/timer_unit.git
     dependencies: []
   udma_camera:
     revision: cfcd80416ef18f8e8139188b8dfa52a8a7f6f7c8
     version: 1.1.2
     source:
-      Git: "https://github.com/pulp-platform/udma_camera.git"
+      Git: https://github.com/pulp-platform/udma_camera.git
     dependencies:
-      - tech_cells_generic
-      - udma_core
+    - tech_cells_generic
+    - udma_core
   udma_core:
     revision: 7af2db5ea8cee3ecfe8e0e647bbdbc7f58ecb73b
     version: 1.1.2
     source:
-      Git: "https://github.com/pulp-platform/udma_core.git"
+      Git: https://github.com/pulp-platform/udma_core.git
     dependencies:
-      - common_cells
-      - tech_cells_generic
+    - common_cells
+    - tech_cells_generic
   udma_external_per:
     revision: 8674ecd131a173915a69ee9e4a04edf8745cbcf4
     version: 1.0.4
     source:
-      Git: "https://github.com/pulp-platform/udma_external_per.git"
+      Git: https://github.com/pulp-platform/udma_external_per.git
     dependencies:
-      - udma_core
+    - udma_core
   udma_filter:
     revision: a11e2057e7b21852e978b744714c384de49228cf
     version: 1.0.3
     source:
-      Git: "https://github.com/pulp-platform/udma_filter.git"
+      Git: https://github.com/pulp-platform/udma_filter.git
     dependencies:
-      - udma_core
+    - udma_core
   udma_hyper:
     revision: 83ab704f9d1c5f9e5353268c901fe95c36bcea36
-    version: ~
+    version: null
     source:
-      Git: "https://github.com/pulp-platform/udma_hyper.git"
+      Git: https://github.com/pulp-platform/udma_hyper.git
     dependencies: []
   udma_i2c:
     revision: 7b84fdb22b9c562528781a40b303ab8ef80c4c9a
     version: 1.0.3
     source:
-      Git: "https://github.com/pulp-platform/udma_i2c.git"
+      Git: https://github.com/pulp-platform/udma_i2c.git
     dependencies:
-      - udma_core
+    - udma_core
   udma_i2s:
     revision: f63cb528dbff7d580c87fd4de90dbdf0ab69048e
     version: 1.1.2
     source:
-      Git: "https://github.com/pulp-platform/udma_i2s.git"
+      Git: https://github.com/pulp-platform/udma_i2s.git
     dependencies:
-      - common_cells
-      - tech_cells_generic
-      - udma_core
+    - common_cells
+    - tech_cells_generic
+    - udma_core
   udma_qspi:
     revision: ddbe8a2e530a5edafc93fe1a25f47fb4b8716bd8
     version: 1.0.4
     source:
-      Git: "https://github.com/pulp-platform/udma_qspi.git"
+      Git: https://github.com/pulp-platform/udma_qspi.git
     dependencies:
-      - common_cells
-      - tech_cells_generic
-      - udma_core
+    - common_cells
+    - tech_cells_generic
+    - udma_core
   udma_sdio:
     revision: e768162ef48ad8fd873daa995ac51269fc82ec4f
     version: 1.1.2
     source:
-      Git: "https://github.com/pulp-platform/udma_sdio.git"
+      Git: https://github.com/pulp-platform/udma_sdio.git
     dependencies:
-      - common_cells
-      - tech_cells_generic
-      - udma_core
+    - common_cells
+    - tech_cells_generic
+    - udma_core
   udma_uart:
     revision: 18ed1986fd62920b1065005c370fd740995cfd4a
     version: 1.0.2
     source:
-      Git: "https://github.com/pulp-platform/udma_uart.git"
+      Git: https://github.com/pulp-platform/udma_uart.git
     dependencies:
-      - common_cells
-      - udma_core
+    - common_cells
+    - udma_core
+  zeroriscy:
+    revision: cc4068a0ccb7691cd062b809c34b2304e7fbfa36
+    version: null
+    source:
+      Git: https://github.com/yvantor/ibex.git
+    dependencies: []
diff --git a/Bender.yml b/Bender.yml
index 774afb96..df373b85 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -10,12 +10,12 @@ package:
     - "Francesco Conti <f.conti@unibo.it>"
 
 dependencies:
-  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git", version: 1.22.1 }
-  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: 0.2.6 }
-  jtag_pulp:          { git: "https://github.com/pulp-platform/jtag_pulp.git", version: 0.1.0 }
-  pulp_soc:           { git: "https://github.com/pulp-platform/pulp_soc.git", version: ~3.0.0 }
-  pulp_cluster:       { git: "https://github.com/pulp-platform/pulp_cluster.git", rev: "db2e173b8b7562092fb9d922d64e0a7bd21da411" }
-  tbtools:            { git: "https://github.com/pulp-platform/tbtools.git", version: 0.2.1 }
+  common_cells:       { git: "https://github.com/pulp-platform/common_cells.git", version: =1.22.1 }
+  tech_cells_generic: { git: "https://github.com/pulp-platform/tech_cells_generic.git", version: =0.2.6 }
+  jtag_pulp:          { git: "https://github.com/pulp-platform/jtag_pulp.git", version: =0.2.0 }
+  pulp_soc:           { git: "git@github.com:FondazioneChipsIT/pulp_soc.git", rev: "a6967f9d654f1754e0564f9947e3a88409747ab7" }
+  pulp_cluster:       { git: "git@github.com:FondazioneChipsIT/pulp_cluster.git", rev: "23cf745df8c86b92ae9171e68de85e074e49dc8b" } #cc_rg/vcu118
+  tbtools:            { git: "https://github.com/pulp-platform/tbtools.git", version: =0.2.1 }
 
 export_include_dirs:
   - rtl/includes
diff --git a/Makefile b/Makefile
index abd4a52c..da689fc6 100644
--- a/Makefile
+++ b/Makefile
@@ -12,6 +12,10 @@ export IPS_PATH=$(PULP_PATH)/fe/ips
 export RTL_PATH=$(PULP_PATH)/fe/rtl
 export TB_PATH=$(PULP_PATH)/rtl/tb
 
+ROOT_DIR = $(strip $(shell dirname $(realpath $(lastword $(MAKEFILE_LIST)))))
+BENDER_GIT_DIR=$(PULP_PATH)/.bender/git/checkouts
+BENDER_BIN := $(shell which bender)
+
 define declareInstallFile
 
 $(VSIM_PATH)/$(1): sim/$(1)
@@ -35,18 +39,23 @@ VLOG_ARGS += -suppress 2583 -suppress 13314 \"+incdir+\$$ROOT/rtl/includes\"
 BENDER_SIM_BUILD_DIR = sim
 BENDER_FPGA_SCRIPTS_DIR = fpga/pulp/tcl/generated
 
+CompileFlags := +acc -permissive -suppress 2583 -suppress 13314 -suppress vlog-1952
+
+VENV := venv
+
 .PHONY: checkout
 ifndef IPAPPROX
 Bender.lock: bender
 	./bender checkout
 	touch Bender.lock
 
-checkout: bender Bender.lock
+checkout: bender
+	./bender checkout
+	touch Bender.lock
 else
 checkout:
 	./update-ips
 endif
-	$(MAKE) scripts
 
 # generic clean and build targets for the platform
 .PHONY: clean
@@ -59,16 +68,32 @@ clean:
 ifndef IPAPPROX
 scripts: scripts-bender-vsim scripts-bender-fpga
 
+include bender-common.mk
+include bender-synth.mk
+
+scripts-bender-vsim-mchan: | Bender.lock
+	echo 'set ROOT [file normalize [file dirname [info script]]/..]' > $(BENDER_SIM_BUILD_DIR)/compile.tcl
+	./bender script vsim \
+		--vlog-arg="$(VLOG_ARGS)" --vcom-arg="" \
+		-t rtl -t test -t pulp -t mchan $(common_defs) $(common_targs) \
+		| grep -v "set ROOT" >> $(BENDER_SIM_BUILD_DIR)/compile.tcl \
+
 scripts-bender-vsim: | Bender.lock
 	echo 'set ROOT [file normalize [file dirname [info script]]/..]' > $(BENDER_SIM_BUILD_DIR)/compile.tcl
 	./bender script vsim \
 		--vlog-arg="$(VLOG_ARGS)" --vcom-arg="" \
-		-t rtl -t test \
-		| grep -v "set ROOT" >> $(BENDER_SIM_BUILD_DIR)/compile.tcl
+		-t rtl -t test -t pulp -t idma $(common_defs) $(common_targs) \
+		| grep -v "set ROOT" >> $(BENDER_SIM_BUILD_DIR)/compile.tcl \
+
+scripts-bender-fpga-mchan: | Bender.lock
+	mkdir -p fpga/pulp/tcl/generated
+	./bender script vivado -t fpga -t mchan -t rtl $(fpga_defs) $(common_defs) $(common_targs) -t xilinx > $(BENDER_FPGA_SCRIPTS_DIR)/compile.tcl
+	sed -i '/TRACE_EXECUTION/d' $(BENDER_FPGA_SCRIPTS_DIR)/compile.tcl
 
 scripts-bender-fpga: | Bender.lock
 	mkdir -p fpga/pulp/tcl/generated
-	./bender script vivado -t fpga -t xilinx > $(BENDER_FPGA_SCRIPTS_DIR)/compile.tcl
+	./bender script vivado -t fpga -t idma -t rtl $(fpga_defs) $(common_defs) $(common_targs) -t xilinx > $(BENDER_FPGA_SCRIPTS_DIR)/compile.tcl
+	sed -i '/TRACE_EXECUTION/d' $(BENDER_FPGA_SCRIPTS_DIR)/compile.tcl
 
 $(BENDER_SIM_BUILD_DIR)/compile.tcl: Bender.lock
 	echo 'set ROOT [file normalize [file dirname [info script]]/..]' > $(BENDER_SIM_BUILD_DIR)/compile.tcl
@@ -92,6 +117,11 @@ scripts-bender-vsim-psram: | Bender.lock
 		| grep -v "set ROOT" >> $(BENDER_SIM_BUILD_DIR)/compile.tcl
 	sed -i 's/psram_fake.v/*.vp_modelsim/g' $(BENDER_SIM_BUILD_DIR)/compile.tcl # Workaround for unsupported file type in bender
 
+$(BENDER_SIM_BUILD_DIR)/compile_lint.tcl:
+	echo 'set ROOT $(ROOT_DIR)' > $(BENDER_SIM_BUILD_DIR)/compile_lint.tcl
+	./bender script vsim --vlog-arg="$(VLOG_ARGS_LINT)" $(common_defs) $(common_targs) $(synth_targs) $(synth_defs) | grep -v "set ROOT" >> $@
+	echo >> $(BENDER_SIM_BUILD_DIR)/compile_lint.tcl
+
 else
 scripts:
 	./generate-scripts
@@ -111,8 +141,23 @@ else
 	./generate-scripts --psram-vip
 endif
 
+venv:
+	python3 -m venv $(VENV) && \
+	$(VENV)/bin/python -m pip install -U pip && \
+	$(VENV)/bin/python -m pip install -r $(shell bender path idma)/requirements.txt
+
+generate_idma_rtl: venv
+	. "$(VENV)/bin/activate" && $(MAKE) -C $(shell bender path idma) idma_hw_all
+
 .PHONY: build
 ## Build the RTL model for vsim
+
+# Init rules: choose to initialize the repo for RTL or FPGA
+
+init: checkout generate_idma_rtl scripts-bender-vsim
+
+init-fpga: checkout generate_idma_rtl scripts-bender-fpga
+
 ifndef IPAPPROX
 build: $(BENDER_SIM_BUILD_DIR)/compile.tcl
 	@test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; }
@@ -124,6 +169,13 @@ build:
 	$(MAKE) -C sim IPAPPROX=$(IPAPPROX) all
 endif
 
+## Build the RTL model for QuestaONE
+build_qone: $(BENDER_SIM_BUILD_DIR)/compile.tcl
+	@test -f Bender.lock || { echo "ERROR: Bender.lock file does not exist. Did you run make checkout in bender mode?"; exit 1; }
+	@test -f $(BENDER_SIM_BUILD_DIR)/compile.tcl || { echo "ERROR: sim/compile.tcl file does not exist. Did you run make scripts in bender mode?"; exit 1; }
+	$(MAKE) -C sim all_qone
+
+
 # sdk specific targets
 install: $(INSTALL_HEADERS)
 
@@ -138,6 +190,26 @@ import_bootcode:
 # continuous integration on jenkins
 all: checkout build install vopt sdk
 
+pulp_sdk:
+	git clone https://github.com/FondazioneChipsIT/pulp-sdk.git; \
+	cd pulp-sdk; \
+	git checkout 362d4d3df37e245455b33790b71f01ecf2261261; \
+	git submodule update --init --recursive;
+
+gvsoc:
+	git clone https://github.com/FondazioneChipsIT/gvsoc.git; \
+	cd gvsoc; \
+	git checkout 71d31e53e36baf6b85a02349f1402b99ef71482c; \
+	git submodule update --init --recursive;
+
+deeploy:
+	git clone https://github.com/FondazioneChipsIT/Deeploy.git; \
+	cd Deeploy; \
+	git checkout 43c3335732db2c59bc7148a22ca16a02365a188e; \
+	git submodule update --init --recursive; \
+	pip install -e . --extra-index-url=https://pypi.ngc.nvidia.com; \
+	make minimalloc xtensor; \
+
 sdk:
 	if [ ! -e pulp-builder ]; then \
 	  git clone --recurse https://github.com/pulp-platform/pulp-builder.git; \
@@ -169,9 +241,15 @@ test:
 sdk-gitlab:
 	sdk-releases/get-sdk-2019.11.03-CentOS_7.py; \
 
-# simplified runtime for PULP that doesn't need the sdk
+## Clone pulp-runtime as SW stack
 pulp-runtime:
-	git clone https://github.com/pulp-platform/pulp-runtime.git -b v0.0.15
+	git clone https://github.com/FondazioneChipsIT/pulp-runtime.git $@
+	cd $@; git checkout ab958e06b37bc05b981dabca9680f72660b8dee1; cd ..
+
+## Clone regression tests for bare-metal verification
+regression-tests:
+	git clone https://github.com/FondazioneChipsIT/regression_tests.git $@
+	cd $@; git checkout 6fac940e924c7de83b37d7be14bfd9febbf04678; cd ..
 
 # the gitlab runner needs a special configuration to be able to access the
 # dependent git repositories
@@ -188,7 +266,7 @@ test-fast-regressions:
 	source pulp-runtime/configs/pulp.sh; \
 	cd regression_tests && ../pulp-runtime/scripts/bwruntests.py --proc-verbose -v --report-junit -t 2000 --yaml -o simplified-runtime.xml simple-regression-tests.yaml
 
-test-local-regressions: 
+test-local-regressions:
 	mkdir -p regression_tests/riscv_tests_soc
 	cp -r regression_tests/riscv_tests/* regression_tests/riscv_tests_soc
 	source setup/vsim.sh; \
@@ -237,18 +315,34 @@ git-boot:
 	touch regression_tests/boot-runtime.xml; \
 	cd regression_tests && ../pulp-runtime/scripts/bwruntests.py --proc-verbose -v --report-junit -t 7200 --yaml -o boot-runtime.xml hello-test.yaml
 
-test-local-runtime: 
+test-local-runtime:
 	source setup/vsim.sh; \
 	source pulp-runtime/configs/pulp.sh; \
 	cd tests && ../pulp-runtime/scripts/bwruntests.py --proc-verbose -v --report-junit -t 600 --yaml -o simplified-runtime.xml runtime-tests.yaml
 
 bender:
-ifeq (,$(wildcard ./bender))
-	curl --proto '=https' --tlsv1.2 -sSf https://pulp-platform.github.io/bender/init \
-		| bash -s -- 0.25.2
-	touch bender
-endif
+	ln -sf $(BENDER_BIN) bender
 
 .PHONY: bender-rm
 bender-rm:
 	rm -f bender
+
+compile_lint:
+	$(MAKE) -C sim compile_lint
+
+lint:
+	$(MAKE) -C sim lint
+
+cdc:
+	$(MAKE) -C sim cdc
+
+PULP_NONFREE_REMOTE ?= git@gitlab.chips.it:digitalresearchline/chips-restricted/pulp-nonfree.git
+PULP_NONFREE_DIR	?= $(ROOT_DIR)/nonfree
+PULP_NONFREE_COMMIT ?= d7274b2dc90d2e2431ef5f009af58a9ba1afdc91
+
+pulp_nonfree_init:
+	git clone $(PULP_NONFREE_REMOTE) $(PULP_NONFREE_DIR)
+	cd $(PULP_NONFREE_DIR) && git checkout $(PULP_NONFREE_COMMIT)
+
+pulp_nonfree_clean:
+	rm -rf $(PULP_NONFREE_DIR)
diff --git a/README.md b/README.md
index 9341f9ef..24f55236 100644
--- a/README.md
+++ b/README.md
@@ -106,10 +106,24 @@ source setup/vsim.sh
 
 make checkout
 
-make scripts
+make generate_idma_rtl
 
+make scripts-bender-vsim
+```
+
+or alternatively: 
+```
+make init
+```
+which does all of the above. Then, to build the RTL platform for QuestaSim:
+```
 make build
 ```
+To build the RTL platform for QuestaOne:
+```
+make build_qone
+```
+
 **NOTE:** An error might occur running the scripts (*Failed to spawn child process.Too many open files (os error 24).*) while a fix is WIP a workaround is to increase the number of processes avilable to your machine by setting for example ulimit to 4096 (ulimit -n 4096).
 
 This command builds a version of the simulation platform with no dependencies on
@@ -196,6 +210,12 @@ To do this, the `LOAD_L2` parameter of the testbench has to be switched from
 ## PULP-SDK
 
 If you are a software developer, you can find the PULP-SDK here: https://github.com/pulp-platform/pulp-sdk.
+The PULP-SDK can also be cloned with the following:
+```
+make pulp_sdk
+```
+This will automatically point to a stable version of the SDK for the PULP-OPEN platform.
+Once in pulp-sdk refer to the related README.md.
 
 ## PULP platform structure
 After being fully setup as explained in the Getting Started section, this root
@@ -210,6 +230,35 @@ repository is structured as follows:
   contains all tests released with the SDK.
 - `Bender.yml` contains all dependency and source file information for the bender tool.
 
+## GVSOC
+
+GVSOC is now to be treated as a standalone module, no longer to be used a submodule of PULP-SDK.
+It can be cloned with the following command:
+```
+make gvsoc
+```
+Build with the following (once you are inside the gvsoc dir):
+```
+source sourceme.sh
+make build TARGETS=pulp-open
+```
+Once in gvsoc refer to the related README.md.
+
+## DEEPLOY
+
+Deeploy can now be cloned and used inside the pulp top directory.
+The following command clones deeploy, updates its submodules and clones the main dependencies needed for execution on the pulp-open platform. 
+```
+make deeploy
+```
+After having cloned Deeploy and its dependencies, do the following: 
+```
+source setup/deeploy.sh
+```
+This script will set the needed environment variables for Deeploy execution. **IMPORTANT**: this version takes for granted that the llvm toolchain is installed in `/opt/llvm_toolchain`. Also, the strongly suggested gcc versions to be used are `gcc 11.4.0` or `gcc 11.5.0`.
+Once these are done and a configuration has been selected in the sdk, you can refer to the README inside Deeploy for launching tests on the pulp-open platform: both gvsoc and rtl platforms are now supported. They are to be selected inside the individual python testrunners inside Deeploy.
+
+
 ## Requirements
 The RTL platform has the following requirements:
 - Relatively recent Linux-based operating system; we tested *Ubuntu 16.04* and
diff --git a/bender-common.mk b/bender-common.mk
new file mode 100644
index 00000000..1383c1f5
--- /dev/null
+++ b/bender-common.mk
@@ -0,0 +1,16 @@
+# Copyright 2023 ETH Zurich and University of Bologna
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+
+common_defs += -D FEATURE_ICACHE_STAT
+common_targs += -t cv32e40p_use_ff_regfile
+bender_defs += -D TRACE_EXECUTION
+common_defs += -D PRIVATE_ICACHE
+common_defs += -D HIERARCHY_ICACHE_32BIT
+common_defs += -D ICACHE_USE_FF
+common_defs += -D CLUSTER_ALIAS
+fpga_defs += -D PULP_FPGA_EMUL
+
+# common_targs += -t rtl
+# common_targs += -t cluster_standalone
+# common_targs += -t scm_use_fpga_scm
\ No newline at end of file
diff --git a/bender-synth.mk b/bender-synth.mk
new file mode 100644
index 00000000..b39f1146
--- /dev/null
+++ b/bender-synth.mk
@@ -0,0 +1,6 @@
+# bender targets
+synth_targs += -t asic
+synth_targs += -t synthesis
+
+# bender defines
+synth_defs += -D SYNTHESIS
\ No newline at end of file
diff --git a/fpga/pulp-vcu118/constraints/vcu118.xdc b/fpga/pulp-vcu118/constraints/vcu118.xdc
index 142ec81d..c3d0545d 100644
--- a/fpga/pulp-vcu118/constraints/vcu118.xdc
+++ b/fpga/pulp-vcu118/constraints/vcu118.xdc
@@ -25,7 +25,6 @@ create_clock -period 100.000 -name tck -waveform {0.000 50.000} [get_ports pad_j
 set_input_jitter tck 1.000
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets pad_jtag_tck_IBUF_inst/O]
 
-
 # minimize routing delay
 set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tdi]
 set_input_delay -clock tck -clock_fall 5.000 [get_ports pad_jtag_tms]
@@ -148,11 +147,11 @@ set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS12} [get_ports pad_reset]
 ######################################################################
 # JTAG mapping (OK)
 ######################################################################
-set_property -dict {PACKAGE_PIN AY14 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tms]
-set_property -dict {PACKAGE_PIN AY15 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tdi]
-set_property -dict {PACKAGE_PIN AW15 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tdo]
-set_property -dict {PACKAGE_PIN AV15 IOSTANDARD LVCMOS18} [get_ports pad_jtag_tck]
-set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS18} [get_ports pad_jtag_trst]
+set_property -dict {PACKAGE_PIN N28 IOSTANDARD LVCMOS12} [get_ports pad_jtag_tms]
+set_property -dict {PACKAGE_PIN M30 IOSTANDARD LVCMOS12} [get_ports pad_jtag_tdi]
+set_property -dict {PACKAGE_PIN N30 IOSTANDARD LVCMOS12} [get_ports pad_jtag_tdo]
+set_property -dict {PACKAGE_PIN P30 IOSTANDARD LVCMOS12} [get_ports pad_jtag_tck]
+set_property -dict {PACKAGE_PIN P29 IOSTANDARD LVCMOS12} [get_ports pad_jtag_trst]
 
 
 #set_property -dict {PACKAGE_PIN AV16 IOSTANDARD LVCMOS18} [get_ports pad_pmod0_4]
@@ -223,17 +222,17 @@ set_property -dict "PACKAGE_PIN BC11 IOSTANDARD LVCMOS18"   [get_ports FMC_qspi_
 # SDIO mapping (TO CHECK)
 ######################################################################
 # PULP pad_sdio_sdio0 - FPGA N28 - ZCU102 GPIO PMOD HEADER J53.1
-set_property -dict "PACKAGE_PIN N28 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data0]
+set_property -dict "PACKAGE_PIN AY14 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data0]
 # PULP pad_sdio_sdio1 - FPGA M30 - ZCU102 GPIO PMOD HEADER J53.3
-set_property -dict "PACKAGE_PIN M30 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data1]
+set_property -dict "PACKAGE_PIN AY15 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data1]
 # PULP pad_sdio_sdio2 - FPGA N30 - ZCU102 GPIO PMOD HEADER J53.5
-set_property -dict "PACKAGE_PIN N30 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data2]
+set_property -dict "PACKAGE_PIN AW15 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data2]
 # PULP pad_sdio_sdio3 - FPGA P30 - ZCU102 GPIO PMOD HEADER J53.7
-set_property -dict "PACKAGE_PIN P30 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data3]
+set_property -dict "PACKAGE_PIN AV15 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_data3]
 # PULP pad_sdio_cmd - FPGA P29 - ZCU102 GPIO PMOD HEADER J53.2
-set_property -dict "PACKAGE_PIN P29 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_cmd]
+set_property -dict "PACKAGE_PIN AV16 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_cmd]
 # PULP pad_sdio_sck - FPGA L31 - ZCU102 GPIO PMOD HEADER J53.4
-set_property -dict "PACKAGE_PIN L31 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_sck]
+set_property -dict "PACKAGE_PIN AU16 IOSTANDARD LVCMOS18"  [get_ports FMC_sdio_sck]
 
 ######################################################################
 # I2S master mapping (OK)
diff --git a/fpga/pulp-vcu118/rtl/xilinx_pulp.v b/fpga/pulp-vcu118/rtl/xilinx_pulp.v
index 67d9cf69..fef79f19 100644
--- a/fpga/pulp-vcu118/rtl/xilinx_pulp.v
+++ b/fpga/pulp-vcu118/rtl/xilinx_pulp.v
@@ -81,7 +81,6 @@ module xilinx_pulp (
 
   input wire  pad_reset,
 
-  input wire  pad_jtag_trst,
   input wire  pad_jtag_tck,
   input wire  pad_jtag_tdi,
   output wire pad_jtag_tdo,
@@ -96,7 +95,7 @@ module xilinx_pulp (
 
   wire        reset_n;
 
-  assign reset_n = ~pad_reset & pad_jtag_trst;
+  assign reset_n = ~pad_reset & vio_reset;
 
   wire [7:0] s_pad_hyper_dq0;
 
@@ -120,6 +119,25 @@ module xilinx_pulp (
     .O (ref_clk  )
   );
 
+  wire clk_50;
+
+  xlnx_clk_wiz i_xlnx_clk_wiz (
+    .clk_in1 ( ref_clk  ),
+    .reset   ( 1'b0     ),
+    .clk_100 ( ),
+    .clk_50  ( clk_50   ),
+    .clk_20  ( ),
+    .clk_10  ( )
+  );
+
+  
+  wire vio_reset;
+
+  xilinx_vio i_xlnx_vio (
+    .clk(clk_50),
+    .probe_out0(vio_reset)
+  );
+
   pulp #(
     .CORE_TYPE_FC(CORE_TYPE),
     .CORE_TYPE_CL(CORE_TYPE),
@@ -179,7 +197,7 @@ module xilinx_pulp (
     .pad_jtag_tdi   (pad_jtag_tdi   ), //keep
     .pad_jtag_tdo   (pad_jtag_tdo   ), //keep
     .pad_jtag_tms   (pad_jtag_tms   ), //keep
-    .pad_jtag_trst  (1'b1           ), //keep
+    .pad_jtag_trst  (1'b1 	    ), //keep
     
     .pad_xtal_in    (ref_clk        ), //keep
     .pad_bootsel0   (               ), //keep
diff --git a/fpga/pulp/Makefile b/fpga/pulp/Makefile
index 6460b9b7..1eb03ef3 100644
--- a/fpga/pulp/Makefile
+++ b/fpga/pulp/Makefile
@@ -7,7 +7,7 @@ VIVADO ?= vivado
 
 .DEFAULT_GOAL:=help
 
-.PHONY: help all gui ips clean-ips clk clean-clk clean
+.PHONY: help all gui ips clean-ips clk clean-clk clean vio clean-vio
 
 all: ips ## Generate the bitstream for pulpissimo with vivado in batch mode. The vivado invocation command may be overriden with the env variable VIVADO.
 	$(VIVADO) -mode batch -source tcl/run.tcl
@@ -15,18 +15,22 @@ all: ips ## Generate the bitstream for pulpissimo with vivado in batch mode. The
 gui: ips ## Generates the bitstream for pulpissimo with vivado in GUI mode. The vivado invocation command may be overriden with the env variable VIVADO.
 	$(VIVADO) -mode gui -source tcl/run.tcl &
 
-ips: clk ## Synthesizes necessary xilinx IP
+ips: clk vio ## Synthesizes necessary xilinx and vio IPs
 
 clean-ips: clean-clk ## Clean all IPs
 
 clk: ## Synthesizes the Xilinx Clocking Manager IPs
 	$(MAKE) -C ips/xilinx_clk_mngr all BOARD=$(BOARD)
 	$(MAKE) -C ips/xilinx_slow_clk_mngr all BOARD=$(BOARD)
+	$(MAKE) -C ips/xilinx_clk_wiz all BOARD=$(BOARD)
 
 clean-clk: ## Removes all Clocking Wizard IP outputs
 	$(MAKE) -C ips/xilinx_clk_mngr clean
 	$(MAKE) -C ips/xilinx_slow_clk_mngr clean
 
+vio: ## Synthesizes the vio IP
+	$(MAKE) -C ips/vio all BOARD=$(BOARD)
+
 clean: ## Removes all bitstreams, *.log files and vivado related files (rm -rf vivado*)
 	rm -rf ${PROJECT}.*[^'bit']
 	rm -rf ${PROJECT}.*[^'bin']
diff --git a/fpga/pulp/ips/vio/.gitignore b/fpga/pulp/ips/vio/.gitignore
new file mode 100644
index 00000000..723290b7
--- /dev/null
+++ b/fpga/pulp/ips/vio/.gitignore
@@ -0,0 +1,20 @@
+#Ignore vivado project files generated by the tcl script
+**/.Xil/*
+**/reports/*
+**/*.cache/*
+**/*.hw/*
+**/*.ip_user_files/*
+**/*.runs/*
+**/*.sim/*
+**/*.srcs/*
+*.edf
+*.xpr
+*.jou
+*.log
+
+.cxl.*
+
+*ip
+
+*_stub.v
+gmon.out
\ No newline at end of file
diff --git a/fpga/pulp/ips/vio/Makefile b/fpga/pulp/ips/vio/Makefile
new file mode 100644
index 00000000..159cbe99
--- /dev/null
+++ b/fpga/pulp/ips/vio/Makefile
@@ -0,0 +1,34 @@
+PROJECT:=xilinx_vio
+VIVADO ?= vivado
+VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
+MODE=batch
+
+ifdef BOARD
+	include ../../../pulp-$(BOARD)/fpga-settings.mk
+endif
+
+.DEFAULT_GOAL:=help
+
+.PHONY: help all gui clean
+
+all: MODE=batch ## Create and synthesize the IP in batch mode.
+
+gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
+
+all gui: $(PROJECT).xpr
+
+$(PROJECT).xpr: ../../../pulp-$(BOARD)/fpga-settings.mk tcl/run.tcl
+	$(MAKE) clean
+	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
+
+clean: ## Remove all build products
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
+
+help: ## Shows this help message
+	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulp/ips/vio/tcl/run.tcl b/fpga/pulp/ips/vio/tcl/run.tcl
new file mode 100644
index 00000000..01d97f01
--- /dev/null
+++ b/fpga/pulp/ips/vio/tcl/run.tcl
@@ -0,0 +1,19 @@
+source ../../tcl/common.tcl
+
+set ipName xilinx_vio
+
+create_project $ipName . -part $partNumber
+set_property board_part $XILINX_BOARD [current_project]
+
+create_ip -name vio -vendor xilinx.com -library ip -version 3.0 -module_name $ipName
+set_property -dict [list \
+                        CONFIG.C_NUM_PROBE_OUT {1} \
+                        CONFIG.C_PROBE_OUT0_INIT_VAL {0x1} \
+                        CONFIG.C_EN_PROBE_IN_ACTIVITY {0} \
+                        CONFIG.C_NUM_PROBE_IN {0} \
+                    ] [get_ips $ipName]
+
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 12 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/fpga/pulp/ips/xilinx_clk_wiz/Makefile b/fpga/pulp/ips/xilinx_clk_wiz/Makefile
new file mode 100644
index 00000000..97875752
--- /dev/null
+++ b/fpga/pulp/ips/xilinx_clk_wiz/Makefile
@@ -0,0 +1,34 @@
+PROJECT:=xilinx_clk_wiz
+VIVADO ?= vivado
+VIVADOFLAGS ?= -nojournal -mode batch -source scripts/prologue.tcl
+MODE=batch
+
+ifdef BOARD
+	include ../../../pulp-$(BOARD)/fpga-settings.mk
+endif
+
+.DEFAULT_GOAL:=help
+
+.PHONY: help all gui clean
+
+all: MODE=batch ## Create and synthesize the IP in batch mode.
+
+gui: MODE=gui  ## Create and synthesize the IP in GUI mode.
+
+all gui: $(PROJECT).xpr
+
+$(PROJECT).xpr: ../../../pulp-$(BOARD)/fpga-settings.mk tcl/run.tcl
+	$(MAKE) clean
+	$(VIVADO) -mode $(MODE) -source tcl/run.tcl
+
+clean: ## Remove all build products
+	rm -rf ${PROJECT}.*
+	rm -rf component.xml
+	rm -rf vivado*.jou
+	rm -rf vivado*.log
+	rm -rf vivado*.str
+	rm -rf xgui
+	rm -rf .Xil
+
+help: ## Shows this help message
+	@grep -E -h '^[a-zA-Z0-9_-]+:.*?## .*$$' $(MAKEFILE_LIST) | sort | awk 'BEGIN {FS = ":.*?## "}; {printf "\033[36m%-30s\033[0m %s\n", $$1, $$2}'
diff --git a/fpga/pulp/ips/xilinx_clk_wiz/tcl/run.tcl b/fpga/pulp/ips/xilinx_clk_wiz/tcl/run.tcl
new file mode 100644
index 00000000..764dd617
--- /dev/null
+++ b/fpga/pulp/ips/xilinx_clk_wiz/tcl/run.tcl
@@ -0,0 +1,52 @@
+# Copyright 2023 ETH Zurich and University of Bologna.
+# Solderpad Hardware License, Version 0.51, see LICENSE for details.
+# SPDX-License-Identifier: SHL-0.51
+#
+# Cyril Koenig <cykoenig@iis.ee.ethz.ch>
+
+source ../../tcl/common.tcl
+
+set ipName xlnx_clk_wiz
+
+create_project $ipName . -force -part $partNumber
+set_property board_part $XILINX_BOARD [current_project]
+
+create_ip -name clk_wiz -vendor xilinx.com -library ip -version 6.0 -module_name $ipName
+
+set_property -dict  [list CONFIG.PRIM_SOURCE {No_buffer} \
+                            CONFIG.PRIM_IN_FREQ {125.000} \
+                            CONFIG.CLKOUT1_USED {true} \
+                            CONFIG.CLKOUT2_USED {true} \
+                            CONFIG.CLKOUT3_USED {true} \
+                            CONFIG.CLKOUT4_USED {true} \
+                            CONFIG.CLK_OUT1_PORT {clk_100} \
+                            CONFIG.CLK_OUT2_PORT {clk_50} \
+                            CONFIG.CLK_OUT3_PORT {clk_20} \
+                            CONFIG.CLK_OUT4_PORT {clk_10} \
+                            CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {100.000} \
+                            CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {50.000} \
+                            CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {20.000} \
+                            CONFIG.CLKOUT4_REQUESTED_OUT_FREQ {10.000} \
+                            CONFIG.CLKIN1_JITTER_PS {33.330000000000005} \
+                            CONFIG.MMCM_CLKFBOUT_MULT_F {4.000} \
+                            CONFIG.MMCM_CLKIN1_PERIOD {8.0} \
+                            CONFIG.MMCM_CLKOUT1_DIVIDE {12} \
+                            CONFIG.MMCM_CLKOUT2_DIVIDE {24} \
+                            CONFIG.MMCM_CLKOUT3_DIVIDE {60} \
+                            CONFIG.MMCM_CLKOUT4_DIVIDE {120} \
+                            CONFIG.NUM_OUT_CLKS {4} \
+                            CONFIG.CLKOUT1_JITTER {134.506} \
+                            CONFIG.CLKOUT1_PHASE_ERROR {154.678} \
+                            CONFIG.CLKOUT2_JITTER {153.164} \
+                            CONFIG.CLKOUT2_PHASE_ERROR {154.678} \
+                            CONFIG.CLKOUT3_JITTER {184.746} \
+                            CONFIG.CLKOUT3_PHASE_ERROR {154.678} \
+                            CONFIG.CLKOUT4_JITTER {213.887} \
+                            CONFIG.CLKOUT4_PHASE_ERROR {154.678} \
+                    ] [get_ips $ipName]
+
+generate_target {instantiation_template} [get_files ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+generate_target all [get_files  ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+create_ip_run [get_files -of_objects [get_fileset sources_1] ./$ipName.srcs/sources_1/ip/$ipName/$ipName.xci]
+launch_run -jobs 8 ${ipName}_synth_1
+wait_on_run ${ipName}_synth_1
\ No newline at end of file
diff --git a/fpga/pulp/tcl/run.tcl b/fpga/pulp/tcl/run.tcl
index 2e35f2cf..4c6192ea 100644
--- a/fpga/pulp/tcl/run.tcl
+++ b/fpga/pulp/tcl/run.tcl
@@ -6,20 +6,18 @@ set CONSTRS constraints
 set FPGA_RTL rtl
 set FPGA_IPS ips
 
+
+# It fixes the long delays during update_compile_order step
+set_param project.hsv.draftModeDefault only
+
 # create project
 create_project $PROJECT . -force -part $::env(XILINX_PART)
 set_property board_part $XILINX_BOARD [current_project]
+set_property XPM_LIBRARIES XPM_MEMORY [current_project]
 
 # Add sources
 source tcl/add_sources.tcl
 
-# Set Verilog Defines.
-set DEFINES "FPGA_TARGET_XILINX=1 TARGET_FPGA=1 TARGET_XILINX=1 PULP_FPGA_EMUL=1 AXI4_XCHECK_OFF=1"
-if { $BOARD == "zcu102" } {
-    set DEFINES "$DEFINES zcu102=1"
-}
-set_property verilog_define $DEFINES [current_fileset]
-
 # detect target clock
 if [info exists ::env(FC_CLK_PERIOD_NS)] {
     set FC_CLK_PERIOD_NS $::env(FC_CLK_PERIOD_NS)
@@ -34,6 +32,8 @@ add_files -norecurse ../pulp-$BOARD/rtl/xilinx_pulp.v
 # Add Xilinx IPs
 read_ip $FPGA_IPS/xilinx_clk_mngr/xilinx_clk_mngr.srcs/sources_1/ip/xilinx_clk_mngr/xilinx_clk_mngr.xci
 read_ip $FPGA_IPS/xilinx_slow_clk_mngr/xilinx_slow_clk_mngr.srcs/sources_1/ip/xilinx_slow_clk_mngr/xilinx_slow_clk_mngr.xci
+read_ip $FPGA_IPS/vio/xilinx_vio.srcs/sources_1/ip/xilinx_vio/xilinx_vio.xci
+read_ip $FPGA_IPS/xilinx_clk_wiz/xlnx_clk_wiz.srcs/sources_1/ip/xlnx_clk_wiz/xlnx_clk_wiz.xci
 
 # set pulp as top
 set_property top xilinx_pulp [current_fileset]; #
@@ -44,8 +44,6 @@ update_compile_order -fileset sources_1
 # Add constraints
 add_files -fileset constrs_1 -norecurse ../pulp-$BOARD/$CONSTRS/$BOARD.xdc
 
-auto_detect_xpm
-
 # Elaborate design
 synth_design -rtl -name rtl_1 -gated_clock_conversion on -sfcu;# sfcu -> run synthesis in single file compilation unit mode
 
diff --git a/rtl/includes/pulp_soc_defines.sv b/rtl/includes/pulp_soc_defines.sv
index 34793667..712ef9ec 100644
--- a/rtl/includes/pulp_soc_defines.sv
+++ b/rtl/includes/pulp_soc_defines.sv
@@ -32,9 +32,6 @@
 `define USE_L2_MULTIBANK
 `define NB_L2_CHANNELS 4
 
-// JTAG
-`define DMI_JTAG_IDCODE 32'h249511C3
-
 // Hardware Accelerator selection
 `define HWCRYPT
 
@@ -51,10 +48,34 @@
 // remember to change the defines in the pulp.h as well to be coherent with this approach
 //`define DEM_PER_BEFORE_TCDM_TS
 
+// Default JTAG ID code type
+typedef struct packed {
+  bit [ 3:0]  version;
+  bit [15:0]  part_num;
+  bit [10:0]  manufacturer;
+  bit         _one;
+} jtag_idcode_t;
+
+// PULP Platform manufacturer and default PulpOpen part number
+localparam bit [10:0] JtagPulpManufacturer  = 11'h6d9;
+localparam bit [15:0] JtagPulpOpenPartNum   = 16'hc5e5;
+localparam bit [ 3:0] JtagPulpOpenVersion   = 4'h1;
+localparam jtag_idcode_t PulpOpenIdCode = '{
+  _one          : 1,
+  manufacturer  : JtagPulpManufacturer,
+  part_num      : JtagPulpOpenPartNum,
+  version       : JtagPulpOpenVersion
+};
+
+// JTAG
+`define DMI_JTAG_IDCODE PulpOpenIdCode
+
 
 
 // uncomment if FPGA emulator
-// `define PULP_FPGA_EMUL 1
+`ifdef TARGET_FPGA
+`define PULP_FPGA_EMUL 1
+`endif
 // uncomment if using Vivado for ulpcluster synthesis
 `define VIVADO
 
@@ -92,7 +113,7 @@
 `define NB_CORES      8
 `define NB_DMAS       4
 `define NB_MPERIPHS   1
-`define NB_SPERIPHS   10
+`define NB_SPERIPHS   12
 //`define REMAP_ADDRESS
 
 `define GPIO_NUM     64 
@@ -101,8 +122,6 @@
 // DEFINES
 `define MPER_EXT_ID   0
 
-
-
 `define RVT 0
 `define LVT 1
 
diff --git a/rtl/pulp/cluster_domain.sv b/rtl/pulp/cluster_domain.sv
index 5c29df20..66d49813 100644
--- a/rtl/pulp/cluster_domain.sv
+++ b/rtl/pulp/cluster_domain.sv
@@ -20,6 +20,8 @@
 
 `include "pulp_soc_defines.sv"
 `include "cluster_bus_defines.sv"
+import pulp_cluster_package::*;
+import axi_pkg::*;
 
 
 module cluster_domain
@@ -205,78 +207,154 @@ module cluster_domain
                                                      `endif
    
    );
+
+  localparam bit[AXI_ADDR_WIDTH-1:0] ClustBase       = 'h10000000;
+  localparam bit[AXI_ADDR_WIDTH-1:0] ClustPeriphOffs = 'h00200000;
+  localparam bit[AXI_ADDR_WIDTH-1:0] ClustExtOffs    = 'h00400000;
+  localparam bit[      5:0] ClustIdx        = 'h0;
+  localparam bit[AXI_ADDR_WIDTH-1:0] ClustBaseAddr   = ClustBase;
+  localparam bit[AXI_ADDR_WIDTH-1:0] L2BaseAddr      = 'h1C000000;
+  localparam bit[AXI_ADDR_WIDTH-1:0] L2Size          = 'h00100000;
+  localparam bit[AXI_ADDR_WIDTH-1:0] BootAddr        = L2BaseAddr + 'h8080;
+  localparam bit[AXI_ADDR_WIDTH-1:0] ClustReturnInt  = 'h10200100;
+
+
+  localparam pulp_cluster_cfg_t PulpClusterCfg = '{
+    CoreType: pulp_cluster_package::RI5CY,
+    NumCores: `NB_CORES,
+    DmaNumPlugs: `NB_DMAS,
+    DmaNumOutstandingBursts: 8,
+    DmaBurstLength: 5,
+    NumMstPeriphs: `NB_MPERIPHS,
+    NumSlvPeriphs: `NB_SPERIPHS,
+    ClusterAlias: 1,
+    ClusterAliasBase: 'h0,
+    NumSyncStages: 3,
+    UseHci: 1,
+    TcdmSize: TCDM_SIZE,
+    TcdmNumBank: 16,
+    HwpePresent: 1,
+    HwpeCfg: '{NumHwpes: 3, HwpeList: {SOFTEX, NEUREKA, REDMULE}},
+    HwpeNumPorts: 9,
+    HMRPresent: 1,
+    HMRDmrEnabled: 1,
+    HMRTmrEnabled: 1,
+    HMRDmrFIxed: 0,
+    HMRTmrFIxed: 0,
+    HMRInterleaveGrps: 1,
+    HMREnableRapidRecovery: 1,
+    HMRSeparateDataVoters: 1,
+    HMRSeparateAxiBus: 0,
+    HMRNumBusVoters: 1,
+    EnableECC: 0,
+    ECCInterco: 0,
+    iCacheNumBanks: 2,
+    iCacheNumLines: 1,
+    iCacheNumWays: 4,
+    iCacheSharedSize: 4*1024,
+    iCachePrivateSize: 512,
+    iCachePrivateDataWidth: 32,
+    EnableReducedTag: 1,
+    L2Size: 1000*1024,
+    DmBaseAddr: 'h60203000,
+    BootRomBaseAddr: 32'h1C008080,
+    BootAddr:  32'h1C008080,
+    EnablePrivateFpu: 1,
+    EnablePrivateFpDivSqrt: 0,
+    NumAxiIn: NumAxiSubordinatePorts,
+    NumAxiOut: NumAxiManagerPorts,
+    AxiIdInWidth: AXI_ID_IN_WIDTH,
+    AxiIdOutWidth: AXI_ID_OUT_WIDTH,
+    AxiAddrWidth: AXI_ADDR_WIDTH,
+    AxiDataInWidth: AXI_DATA_S2C_WIDTH,
+    AxiDataOutWidth: AXI_DATA_C2S_WIDTH,
+    AxiUserWidth: AXI_USER_WIDTH,
+    AxiMaxInTrans: 64,
+    AxiMaxOutTrans: 64,
+    AxiCdcLogDepth: 3,
+    AxiCdcSyncStages: 3,
+    SyncStages: 3,
+    ClusterBaseAddr: ClustBaseAddr,
+    ClusterPeriphOffs: ClustPeriphOffs,
+    ClusterExternalOffs: ClustExtOffs,
+    EnableRemapAddress: 0,
+    SnitchICache: 0,
+    default: '0
+  };
    
     pulp_cluster
 `ifndef USE_CLUSTER_NETLIST
     #(
-        .CORE_TYPE_CL                 ( CORE_TYPE_CL                 ),
-        .NB_CORES                     ( NB_CORES                     ),
-        .NB_HWPE_PORTS                ( NB_HWPE_PORTS                ),
-        .NB_DMAS                      ( NB_DMAS                      ),
-        .TCDM_SIZE                    ( TCDM_SIZE                    ),
-        .NB_TCDM_BANKS                ( NB_TCDM_BANKS                ),
-        .TCDM_BANK_SIZE               ( TCDM_BANK_SIZE               ),
-        .TCDM_NUM_ROWS                ( TCDM_NUM_ROWS                ),
-        .HWPE_PRESENT                 ( USE_HWPE_CL                  ),
-        .SET_ASSOCIATIVE              ( SET_ASSOCIATIVE              ),
-        .NB_CACHE_BANKS               ( NB_CACHE_BANKS               ),
-        .CACHE_LINE                   ( CACHE_LINE                   ),
-        .CACHE_SIZE                   ( CACHE_SIZE                   ),
-        .ICACHE_DATA_WIDTH            ( ICACHE_DATA_WIDTH            ),
-        .L0_BUFFER_FEATURE            ( L0_BUFFER_FEATURE            ),
-        .MULTICAST_FEATURE            ( MULTICAST_FEATURE            ),
-        .SHARED_ICACHE                ( SHARED_ICACHE                ),
-        .DIRECT_MAPPED_FEATURE        ( DIRECT_MAPPED_FEATURE        ),
-        .L2_SIZE                      ( L2_SIZE                      ),
-        .ROM_BOOT_ADDR                ( ROM_BOOT_ADDR                ),
-        .BOOT_ADDR                    ( BOOT_ADDR                    ),
-        .INSTR_RDATA_WIDTH            ( INSTR_RDATA_WIDTH            ),
-        .CLUST_FPU                    ( CLUST_FPU                    ),
-        .CLUST_FP_DIVSQRT             ( CLUST_FP_DIVSQRT             ),
-        .CLUST_SHARED_FP              ( CLUST_SHARED_FP              ),
-        .CLUST_SHARED_FP_DIVSQRT      ( CLUST_SHARED_FP_DIVSQRT      ),
-        .AXI_ADDR_WIDTH               ( AXI_ADDR_WIDTH               ),
-        .AXI_DATA_C2S_WIDTH           ( AXI_DATA_C2S_WIDTH           ),
-        .AXI_DATA_S2C_WIDTH           ( AXI_DATA_S2C_WIDTH           ),
-        .AXI_USER_WIDTH               ( AXI_USER_WIDTH               ),
-        .AXI_ID_IN_WIDTH              ( AXI_ID_IN_WIDTH              ),
-        .AXI_ID_OUT_WIDTH             ( AXI_ID_OUT_WIDTH             ),
-        .AXI_STRB_C2S_WIDTH           ( AXI_STRB_C2S_WIDTH           ),
-        .AXI_STRB_S2C_WIDTH           ( AXI_STRB_S2C_WIDTH           ),
-        .DC_SLICE_BUFFER_WIDTH        ( DC_SLICE_BUFFER_WIDTH        ),
-        .LOG_DEPTH                    ( LOG_DEPTH                    ),
-        .C2S_AW_WIDTH                 ( C2S_AW_WIDTH                 ),
-        .C2S_W_WIDTH                  ( C2S_W_WIDTH                  ),
-        .C2S_B_WIDTH                  ( C2S_B_WIDTH                  ),
-        .C2S_R_WIDTH                  ( C2S_R_WIDTH                  ),
-        .C2S_AR_WIDTH                 ( C2S_AR_WIDTH                 ),
-        .S2C_AW_WIDTH                 ( S2C_AW_WIDTH                 ),
-        .S2C_W_WIDTH                  ( S2C_W_WIDTH                  ),
-        .S2C_B_WIDTH                  ( S2C_B_WIDTH                  ),
-        .S2C_R_WIDTH                  ( S2C_R_WIDTH                  ),
-        .S2C_AR_WIDTH                 ( S2C_AR_WIDTH                 ),
-        .DATA_WIDTH                   ( DATA_WIDTH                   ),
-        .ADDR_WIDTH                   ( ADDR_WIDTH                   ),
-        .BE_WIDTH                     ( BE_WIDTH                     ),
-        .TEST_SET_BIT                 ( TEST_SET_BIT                 ),
-        .ADDR_MEM_WIDTH               ( ADDR_MEM_WIDTH               ),
-        .TCDM_ADD_WIDTH               ( TCDM_ADD_WIDTH               ),
-        .LOG_CLUSTER                  ( LOG_CLUSTER                  ),
-        .PE_ROUTING_LSB               ( PE_ROUTING_LSB               ),
-        .EVNT_WIDTH                   ( EVNT_WIDTH                   ),
-        .CLUSTER_ALIAS_BASE           ( CLUSTER_ALIAS_BASE           )
+        .Cfg ( PulpClusterCfg                                           )
+        // .CORE_TYPE_CL                 ( CORE_TYPE_CL                 ),
+        // .NB_CORES                     ( NB_CORES                     ),
+        // .NB_HWPE_PORTS                ( NB_HWPE_PORTS                ),
+        // .NB_DMAS                      ( NB_DMAS                      ),
+        // .TCDM_SIZE                    ( TCDM_SIZE                    ),
+        // .NB_TCDM_BANKS                ( NB_TCDM_BANKS                ),
+        // .TCDM_BANK_SIZE               ( TCDM_BANK_SIZE               ),
+        // .TCDM_NUM_ROWS                ( TCDM_NUM_ROWS                ),
+        // .HWPE_PRESENT                 ( USE_HWPE_CL                  ),
+        // .SET_ASSOCIATIVE              ( SET_ASSOCIATIVE              ),
+        // .NB_CACHE_BANKS               ( NB_CACHE_BANKS               ),
+        // .CACHE_LINE                   ( CACHE_LINE                   ),
+        // .CACHE_SIZE                   ( CACHE_SIZE                   ),
+        // .ICACHE_DATA_WIDTH            ( ICACHE_DATA_WIDTH            ),
+        // .L0_BUFFER_FEATURE            ( L0_BUFFER_FEATURE            ),
+        // .MULTICAST_FEATURE            ( MULTICAST_FEATURE            ),
+        // .SHARED_ICACHE                ( SHARED_ICACHE                ),
+        // .DIRECT_MAPPED_FEATURE        ( DIRECT_MAPPED_FEATURE        ),
+        // .L2_SIZE                      ( L2_SIZE                      ),
+        // .ROM_BOOT_ADDR                ( ROM_BOOT_ADDR                ),
+        // .BOOT_ADDR                    ( BOOT_ADDR                    ),
+        // .INSTR_RDATA_WIDTH            ( INSTR_RDATA_WIDTH            ),
+        // .CLUST_FPU                    ( CLUST_FPU                    ),
+        // .CLUST_FP_DIVSQRT             ( CLUST_FP_DIVSQRT             ),
+        // .CLUST_SHARED_FP              ( CLUST_SHARED_FP              ),
+        // .CLUST_SHARED_FP_DIVSQRT      ( CLUST_SHARED_FP_DIVSQRT      ),
+        // .AXI_ADDR_WIDTH               ( AXI_ADDR_WIDTH               ),
+        // .AXI_DATA_C2S_WIDTH           ( AXI_DATA_C2S_WIDTH           ),
+        // .AXI_DATA_S2C_WIDTH           ( AXI_DATA_S2C_WIDTH           ),
+        // .AXI_USER_WIDTH               ( AXI_USER_WIDTH               ),
+        // .AXI_ID_IN_WIDTH              ( AXI_ID_IN_WIDTH              ),
+        // .AXI_ID_OUT_WIDTH             ( AXI_ID_OUT_WIDTH             ),
+        // .AXI_STRB_C2S_WIDTH           ( AXI_STRB_C2S_WIDTH           ),
+        // .AXI_STRB_S2C_WIDTH           ( AXI_STRB_S2C_WIDTH           ),
+        // .DC_SLICE_BUFFER_WIDTH        ( DC_SLICE_BUFFER_WIDTH        ),
+        // .LOG_DEPTH                    ( LOG_DEPTH                    ),
+        // .C2S_AW_WIDTH                 ( C2S_AW_WIDTH                 ),
+        // .C2S_W_WIDTH                  ( C2S_W_WIDTH                  ),
+        // .C2S_B_WIDTH                  ( C2S_B_WIDTH                  ),
+        // .C2S_R_WIDTH                  ( C2S_R_WIDTH                  ),
+        // .C2S_AR_WIDTH                 ( C2S_AR_WIDTH                 ),
+        // .S2C_AW_WIDTH                 ( S2C_AW_WIDTH                 ),
+        // .S2C_W_WIDTH                  ( S2C_W_WIDTH                  ),
+        // .S2C_B_WIDTH                  ( S2C_B_WIDTH                  ),
+        // .S2C_R_WIDTH                  ( S2C_R_WIDTH                  ),
+        // .S2C_AR_WIDTH                 ( S2C_AR_WIDTH                 ),
+        // .DATA_WIDTH                   ( DATA_WIDTH                   ),
+        // .ADDR_WIDTH                   ( ADDR_WIDTH                   ),
+        // .BE_WIDTH                     ( BE_WIDTH                     ),
+        // .TEST_SET_BIT                 ( TEST_SET_BIT                 ),
+        // .ADDR_MEM_WIDTH               ( ADDR_MEM_WIDTH               ),
+        // .TCDM_ADD_WIDTH               ( TCDM_ADD_WIDTH               ),
+        // .LOG_CLUSTER                  ( LOG_CLUSTER                  ),
+        // .PE_ROUTING_LSB               ( PE_ROUTING_LSB               ),
+        // .EVNT_WIDTH                   ( EVNT_WIDTH                   ),
+        // .CLUSTER_ALIAS_BASE           ( CLUSTER_ALIAS_BASE           )
     )
-`endif    
+`endif
     cluster_i
     (
         .clk_i                        ( clk_i                        ),
         .rst_ni                       ( rst_ni                       ),
         .ref_clk_i                    ( ref_clk_i                    ),
+        .pwr_on_rst_ni                ( rst_ni                       ),
+        .mbox_irq_i                   ( '0                           ),
+        .axi_isolate_i                ( '0                           ),
 
         .pmu_mem_pwdn_i               ( 1'b0                         ),
         
-        .base_addr_i                  ( '0                           ),
-        
         .dma_pe_evt_ack_i             ( dma_pe_evt_ack_i             ),
         .dma_pe_evt_valid_o           ( dma_pe_evt_valid_o           ),
         .dma_pe_irq_ack_i             ( dma_pe_irq_ack_i             ),
diff --git a/rtl/pulp/pulp.sv b/rtl/pulp/pulp.sv
index a684d318..ed6d88c8 100644
--- a/rtl/pulp/pulp.sv
+++ b/rtl/pulp/pulp.sv
@@ -93,7 +93,7 @@ module pulp
   localparam AXI_SOC_CLUSTER_ID_WIDTH   = pkg_soc_interconnect::AXI_ID_OUT_WIDTH; // Backrouting through the AXI-XBAR in pulp_soc requries some extra ID bits. Check axi_xbar docu for details
   localparam AXI_CLUSTER_SOC_ID_WIDTH   = AXI_SOC_CLUSTER_ID_WIDTH + $clog2(`NB_SLAVE);
 
-  localparam AXI_USER_WIDTH             = 6;
+  localparam AXI_USER_WIDTH             = 10;
   localparam AXI_CLUSTER_SOC_STRB_WIDTH = AXI_CLUSTER_SOC_DATA_WIDTH/8;
   localparam AXI_SOC_CLUSTER_STRB_WIDTH = AXI_SOC_CLUSTER_DATA_WIDTH/8;
 
@@ -1160,7 +1160,7 @@ cluster_domain#(
         .NB_CORES            (`NB_CORES),
         .NB_HWPE_PORTS       (4),
         .NB_DMAS             (4),
-        .TCDM_SIZE           (64*1024),
+        .TCDM_SIZE           (256*1024),
         .NB_TCDM_BANKS       (16),
         .L2_SIZE             (512*1024),
   // ICACHE PARAMETERS
diff --git a/rtl/tb/tb_fs_handler.sv b/rtl/tb/tb_fs_handler.sv
index ee6df298..75b8ab91 100644
--- a/rtl/tb/tb_fs_handler.sv
+++ b/rtl/tb/tb_fs_handler.sv
@@ -345,4 +345,4 @@ module tb_fs_handler_debug #(
             end
       end
 
-endmodule
+endmodule
\ No newline at end of file
diff --git a/rtl/tb/tb_pulp.sv b/rtl/tb/tb_pulp.sv
index 676692e7..580d0eae 100644
--- a/rtl/tb/tb_pulp.sv
+++ b/rtl/tb/tb_pulp.sv
@@ -105,11 +105,14 @@ module tb_pulp;
    // enable Debug Module Tests
    parameter ENABLE_DM_TESTS = 0;
 
+   // use fast debug preload
+   parameter USE_FAST_DEBUG_PRELOAD = 1;
+
    // use the pulp tap to access the bus
    parameter USE_PULP_BUS_ACCESS = 1;
 
    // UART baud rate in bps
-   parameter  BAUDRATE = 625000;
+   parameter  BAUDRATE = 115200;
 
    // use frequency-locked loop to generate internal clock
    parameter  USE_FLL = 1;
@@ -950,7 +953,11 @@ module tb_pulp;
                end
 
                $display("[TB] %t - Loading L2", $realtime);
-               if (USE_PULP_BUS_ACCESS) begin
+               if(USE_FAST_DEBUG_PRELOAD) begin
+                  $warning("[TB  ] - Preloading the memory via direct simulator access. \nNEVER EVER USE THIS MODE TO VERIFY THE BOOT BEHAVIOR OF A CHIP. THIS BOOTMODE IS IMPOSSIBLE ON A PHYSICAL CHIP!!!");
+                  preload_l2(num_stim, stimuli);
+
+               end else if (USE_PULP_BUS_ACCESS) begin
                   // use pulp tap to load binary 
                   pulp_tap_pkg::load_L2(num_stim, stimuli, s_tck, s_tms, s_trstn, s_tdi, s_tdo);
 
@@ -1081,6 +1088,41 @@ module tb_pulp;
          end
       end
 
+  task automatic preload_l2(input int num_stim, ref logic [95:0] stimuli [100000:0]);
+    logic more_stim;
+    static logic [95:0] stim_entry;
+    more_stim = 1'b1;
+    $display("[TB] %t: Preloading L2 with stimuli through direct access.", $realtime);
+    while (more_stim == 1'b1) begin
+      @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i);
+      stim_entry = stimuli[num_stim];
+      force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.req = 1'b1;
+      force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.add = stim_entry[95:64];
+      force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[31:0];
+      force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wen = 1'b0;
+      force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.be = '1;
+      do begin
+        @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i);
+      end while (~i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.gnt);
+      force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.add   = stim_entry[95:64]+4;
+      force i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wdata = stim_entry[63:32];
+      do begin
+        @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i);
+      end while (~i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.gnt);
+
+      num_stim = num_stim + 1;
+      if (num_stim > $size(stimuli) || stimuli[num_stim] === 96'bx) begin  // make sure we have more stimuli
+        more_stim = 0;  // if not set variable to 0, will prevent additional stimuli to be applied
+        break;
+      end
+    end  // while (more_stim == 1'b1)
+    release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.req;
+    release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.add;
+    release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wdata;
+    release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.wen;
+    release i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.tcdm_debug.be;
+    @(posedge i_dut.soc_domain_i.pulp_soc_i.i_soc_interconnect_wrap.clk_i);
+  endtask
 
 endmodule // tb_pulp
 
diff --git a/setup/deeploy.sh b/setup/deeploy.sh
new file mode 100644
index 00000000..ba346bb2
--- /dev/null
+++ b/setup/deeploy.sh
@@ -0,0 +1,11 @@
+ROOT=$(cd "$(dirname "${BASH_SOURCE[0]:-${(%):-%x}}")/.." && pwd)
+DEEPLOY_ROOT="$ROOT"/Deeploy
+
+export MINIMALLOC_INSTALL_DIR=$DEEPLOY_ROOT/install/minimalloc
+export PULP_SDK_HOME=$ROOT/pulp-sdk
+export GVSOC_INSTALL_DIR=$ROOT/gvsoc/install
+export LLVM_INSTALL_DIR=/opt/llvm_toolchain/llvm
+export GCC_INSTALL_DIR=/opt/riscv/pulp-gcc-1.0.16/
+export CMAKE=/usr/bin/cmake
+export PATH=$ROOT/../../deeploy_gcc/gcc-11.4.0/bin/:$PATH
+export PULP_OPEN_HOME=$ROOT
diff --git a/setup/sdk.sh b/setup/sdk.sh
index 650a27cb..e45f043d 100644
--- a/setup/sdk.sh
+++ b/setup/sdk.sh
@@ -1,4 +1,2 @@
 ROOT=$(cd "$(dirname "${BASH_SOURCE[0]:-${(%):-%x}}")/.." && pwd)
 export VSIM_PATH="$ROOT"/sim
-source pulp-sdk/setup.sh
-source pulp-sdk/sourceme.sh
diff --git a/setup/vsim.sh b/setup/vsim.sh
index e45f043d..027f4118 100644
--- a/setup/vsim.sh
+++ b/setup/vsim.sh
@@ -1,2 +1,3 @@
 ROOT=$(cd "$(dirname "${BASH_SOURCE[0]:-${(%):-%x}}")/.." && pwd)
 export VSIM_PATH="$ROOT"/sim
+export TB_PATH="$ROOT"/rtl/tb
diff --git a/sim/Makefile b/sim/Makefile
index b78152b2..bd5d8a85 100644
--- a/sim/Makefile
+++ b/sim/Makefile
@@ -2,6 +2,10 @@
 
 mkfile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST))))
 
+QOPT ?= qopt
+QSIM ?= qsim
+Q1VE ?= q1ve --qverify
+
 VOPT				?= vopt
 VSIM				?= vsim
 VLIB				?= vlib
@@ -11,7 +15,11 @@ VSIM_FLAGS  = -gUSE_SDVT_SPI=0 -gUSE_SDVT_CPI=0 -gBAUDRATE=115200 \
 
 SVLIB	    =  ../rtl/tb/remote_bitbang/librbs
 
-all: clean lib build opt
+top_level ?= pulp
+
+all: clean build opt
+
+all_qone: clean build_qone opt_qone
 
 # build the bitbang library, needed for simulating a jtag bridge to OpenOCD
 build-deps:
@@ -20,30 +28,51 @@ build-deps:
 clean-deps:
 	$(MAKE) -C ../rtl/tb/remote_bitbang clean
 
+sim_qone:
+	$(QSIM) -qwavedb=+signal+memory -64 -gui vopt_tb -L models_lib -L vip_lib \
+		+UVM_NO_RELNOTES -stats -t ps \
+		-sv_lib $(SVLIB) $(VSIM_FLAGS) \
+		-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1"
+
 sim:
 	$(VSIM) -64 -gui vopt_tb -L models_lib -L vip_lib \
-		-suppress vsim-3009 -suppress vsim-8683 \
 		+UVM_NO_RELNOTES -stats -t ps \
 		-sv_lib $(SVLIB) $(VSIM_FLAGS) \
 		-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1"
 
 simc:
 	$(VSIM) -64 -c vopt_tb -L models_lib -L vip_lib \
-		-suppress vsim-3009 -suppress vsim-8683 \
 		+UVM_NO_RELNOTES -stats -t ps \
 		-sv_lib $(SVLIB) $(VSIM_FLAGS) \
 		-do "set StdArithNoWarnings 1; set NumericStdNoWarnings 1" \
 		-do "run -all" \
 		-do "quit -code [examine -radix decimal sim:/tb_pulp/exit_status]"
 
+opt_qone:
+ifndef IPAPPROX
+	$(QOPT) -debug,livesim +designfile tb_pulp -o vopt_tb -work work
+else
+	$(mkfile_path)/tcl_files/rtl_vopt.tcl
+endif
+
 opt:
 ifndef IPAPPROX
-	$(VOPT) +acc=npr -o vopt_tb tb_pulp -floatparameters+tb_pulp -work work
+	$(VOPT) +acc=npr tb_pulp -o vopt_tb -work work
 else
 	$(mkfile_path)/tcl_files/rtl_vopt.tcl
 endif
 
-build: build-deps
+build_qone:
+# build-deps
+ifndef IPAPPROX
+	$(QSIM) -c -do 'source compile.tcl; quit'
+else
+	@make --no-print-directory -f $(mkfile_path)/vcompile/ips.mk build
+	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl.mk build
+endif
+
+build:
+# build-deps
 ifndef IPAPPROX
 	$(VSIM) -c -do 'source compile.tcl; quit'
 else
@@ -54,14 +83,15 @@ endif
 lib:
 ifndef IPAPPROX
 	@$(VLIB) work
-	@chmod +w modelsim.ini
+# @chmod +w modelsim.ini
 	$(VMAP) work $(mkfile_path)/work
 else
 	@make --no-print-directory -f $(mkfile_path)/vcompile/ips.mk lib
 	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl.mk lib
 endif
 
-clean: clean-deps
+clean:
+# clean-deps
 ifndef IPAPPROX
 	@mkdir -p work
 	rm -r work 
@@ -69,6 +99,33 @@ else
 	@make --no-print-directory -f $(mkfile_path)/vcompile/ips.mk clean
 	@make --no-print-directory -f $(mkfile_path)/vcompile/rtl.mk clean
 endif
-	@touch modelsim.ini
-	@chmod +w modelsim.ini
-	rm modelsim.ini
+# @touch modelsim.ini
+# @chmod +w modelsim.ini
+# rm modelsim.ini
+
+$(library):
+	$(QUESTA) vlib $(library)
+
+compile_lint: $(library)
+	$(Q1VE) -od lint/comp_lint_results -c -do " \
+	onerror {exit}; \
+	do compile_lint.tcl; \
+	exit"
+lint: compile_lint
+	$(Q1VE) -od lint/lint_results -c -do " \
+	lint methodology ip -goal release; \
+	lint run -d $(top_level); \
+	exit"
+
+
+# split rule in different .tcl files
+# add configure message suppress -type generic
+# sdc preference -infer_false_path_domains for false paths in sdc
+# remove multi_fanout_async for now -> until sdc is cleaned
+cdc: compile_lint
+	$(Q1VE) -od cdc_results -c -do " \
+	sdc preference -sta_mode; \
+	sdc load timing.sdc; \
+	cdc preference -multi_fanout_async; \
+	cdc run -d $(top_level); \
+	exit"
diff --git a/sim/tcl_files/config/vsim.tcl b/sim/tcl_files/config/vsim.tcl
index b0e9955b..23595c66 100644
--- a/sim/tcl_files/config/vsim.tcl
+++ b/sim/tcl_files/config/vsim.tcl
@@ -85,13 +85,25 @@ quietly set vsim_custom_args "\
   "
 
 quietly set vopt_args ""
-if {$vopt_acc_ena == "YES"} {
-  #+ quietly append vopt_args $vopt_args "+acc=abflmnprstv"
-  quietly append vopt_args $vopt_args "+acc=mnprv \
+
+# if {$vopt_acc_ena == "YES"} {
+#   #+ quietly append vopt_args $vopt_args "+acc=abflmnprstv"
+#   quietly append vopt_args $vopt_args "+acc=mnprv \
+#                                        -assertdebug \
+#                                        -bitscalars \
+#                                        -fsmdebug \
+#                                        -linedebug"
+# }
+if {[info exists ::env(USE_QONE)] && $::env(USE_QONE) == 1} {
+  quietly append vopt_args $vopt_args ""
+} else {
+  if {$vopt_acc_ena == "YES"} {
+    quietly append vopt_args $vopt_args "+acc=mnprv \
                                        -assertdebug \
                                        -bitscalars \
                                        -fsmdebug \
                                        -linedebug"
+  }
 }
 if {[info exists vopt_cov]} {
   quietly append vopt_args $vopt_args $vopt_cov
@@ -117,15 +129,28 @@ if {[info exists ::env(VOPT_FLOW)]} {
 
 
 } {
-  set vsim_cmd "vsim -c -quiet $TB \
-                -t ps \
-                $vsim_cov \
-                $common_args \
-                $custom_args \
-                $common_sdvt_args \
-                $vsim_custom_args \
-                $vsim_vopt_args \
-                "
+  if {[info exists ::env(USE_QONE)] && $::env(USE_QONE) == 1} {
+    set vsim_cmd "qsim $TB \
+                  -qwavedb=+signal+memory \
+                  -t ps \
+                  $vsim_cov \
+                  $common_args \
+                  $custom_args \
+                  $common_sdvt_args \
+                  $vsim_custom_args \
+                  $vsim_vopt_args \
+                  "
+  } else {
+    set vsim_cmd "vsim -quiet $TB \
+                  -t ps \
+                  $vsim_cov \
+                  $common_args \
+                  $custom_args \
+                  $common_sdvt_args \
+                  $vsim_custom_args \
+                  $vsim_vopt_args \
+                  "
+  }
 
     eval $vsim_cmd
     eval $vsimcmd_test_path
diff --git a/sim/tcl_files/rtl_vopt.tcl b/sim/tcl_files/rtl_vopt.tcl
index 6d00d91e..56c38983 100755
--- a/sim/tcl_files/rtl_vopt.tcl
+++ b/sim/tcl_files/rtl_vopt.tcl
@@ -1,9 +1,5 @@
 #!/usr/bin/env tclsh
 
-source ./tcl_files/config/vsim_ips.tcl
-source ./tcl_files/config/vsim_rtl.tcl
-
-
 proc color {foreground text} {
     # tput is a little Unix utility that lets you use the termcap database
     # *much* more easily...
diff --git a/sim/tcl_files/run.tcl b/sim/tcl_files/run.tcl
index f32d35de..0537630c 100755
--- a/sim/tcl_files/run.tcl
+++ b/sim/tcl_files/run.tcl
@@ -2,4 +2,4 @@
 
 set TB "vopt_tb -L models_lib -L vip_lib"
 
-source ./tcl_files/config/vsim.tcl
+source ${::env(VSIM_PATH)}/tcl_files/config/vsim.tcl
diff --git a/sim/tcl_files/run_gui.tcl b/sim/tcl_files/run_gui.tcl
new file mode 100644
index 00000000..532e276f
--- /dev/null
+++ b/sim/tcl_files/run_gui.tcl
@@ -0,0 +1,5 @@
+#!/bin/bash
+
+set TB "vopt_tb -L models_lib -L vip_lib"
+
+source ${::env(VSIM_PATH)}/tcl_files/config/vsim.tcl
\ No newline at end of file