From 44bbfbaaea6d0be8e30d3b1603b2b8bc30027bba Mon Sep 17 00:00:00 2001 From: Chaitanya Vadrevu Date: Fri, 28 Aug 2026 19:22:47 -0500 Subject: [PATCH 1/2] ARM: dts: zynq: Describe CPU cache hierarchy Describe the Cortex-A9 L1 cache geometry and link both CPUs to the shared PL310 L2 cache. Add the L2 cache geometry as well. This allows the generic cacheinfo framework to expose cache size, line size, set count, associativity, and sharing information through sysfs. Assisted-by: Copilot:GPT-5.6-Sol Signed-off-by: Chaitanya Vadrevu --- arch/arm/boot/dts/xilinx/zynq-7000.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi index 153b8d93cbee2..79b576f8f8298 100644 --- a/arch/arm/boot/dts/xilinx/zynq-7000.dtsi +++ b/arch/arm/boot/dts/xilinx/zynq-7000.dtsi @@ -26,6 +26,13 @@ clocks = <&clkc 3>; clock-latency = <1000>; cpu0-supply = <®ulator_vccpint>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + d-cache-sets = <256>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <256>; + next-level-cache = <&L2>; operating-points = < /* kHz uV */ 666667 1000000 @@ -38,6 +45,13 @@ device_type = "cpu"; reg = <1>; clocks = <&clkc 3>; + d-cache-size = <0x8000>; + d-cache-line-size = <32>; + d-cache-sets = <256>; + i-cache-size = <0x8000>; + i-cache-line-size = <32>; + i-cache-sets = <256>; + next-level-cache = <&L2>; }; }; @@ -191,6 +205,9 @@ arm,tag-latency = <2 2 2>; cache-unified; cache-level = <2>; + cache-size = <0x80000>; + cache-line-size = <32>; + cache-sets = <2048>; }; mc: memory-controller@f8006000 { From ada897062cf7a7eacbaae2031d780949072f5a4d Mon Sep 17 00:00:00 2001 From: Chaitanya Vadrevu Date: Fri, 28 Aug 2026 19:41:16 -0500 Subject: [PATCH 2/2] cacheinfo: Preserve legacy cache size format for NI ARM Released NI ARM software expects cache size attributes in sysfs to be reported as bytes, matching the format provided by older NI kernels. The generic cacheinfo implementation reports sizes with a K suffix, which causes existing LabVIEW CPU information code to interpret a 32K cache as 32 bytes. Add an NI ARM compatibility option that reports cache sizes in bytes and enable it for NI Zynq targets. Other platforms retain the standard generic cacheinfo format. Assisted-by: Copilot:GPT-5.6-Sol Signed-off-by: Chaitanya Vadrevu --- arch/arm/configs/nati_zynq_defconfig | 1 + arch/arm/mach-zynq/Kconfig | 9 +++++++++ drivers/base/cacheinfo.c | 3 +++ 3 files changed, 13 insertions(+) diff --git a/arch/arm/configs/nati_zynq_defconfig b/arch/arm/configs/nati_zynq_defconfig index ad74851ef7245..126a1a6885ddc 100644 --- a/arch/arm/configs/nati_zynq_defconfig +++ b/arch/arm/configs/nati_zynq_defconfig @@ -24,6 +24,7 @@ CONFIG_PERF_EVENTS=y CONFIG_ARCH_VEXPRESS=y CONFIG_ARCH_ZYNQ=y CONFIG_NI_ZYNQ_GIC_LEGACY_IRQDOMAIN=y +CONFIG_NI_LEGACY_ARM_CACHEINFO_SIZE=y CONFIG_ARM_ERRATA_754322=y CONFIG_ARM_ERRATA_764369=y CONFIG_ARM_ERRATA_775420=y diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig index 6335678a1fd28..36b931d862895 100644 --- a/arch/arm/mach-zynq/Kconfig +++ b/arch/arm/mach-zynq/Kconfig @@ -25,3 +25,12 @@ config NI_ZYNQ_GIC_LEGACY_IRQDOMAIN This preserves compatibility with NI drivers that use fixed IRQs. Enable this only on NI Zynq systems that require the legacy IRQ numbering contract. + +config NI_LEGACY_ARM_CACHEINFO_SIZE + bool "Use legacy cache size units on NI ARM targets" + depends on ARCH_ZYNQ + help + Report CPU cache sizes in bytes through sysfs instead of using the + generic cacheinfo K suffix. This preserves compatibility with released + NI ARM software that expects the legacy NI kernel representation. + Enable this only for systems that require this compatibility behavior. diff --git a/drivers/base/cacheinfo.c b/drivers/base/cacheinfo.c index 613410705a47e..72fe6be60d659 100644 --- a/drivers/base/cacheinfo.c +++ b/drivers/base/cacheinfo.c @@ -664,6 +664,9 @@ static ssize_t size_show(struct device *dev, { struct cacheinfo *this_leaf = dev_get_drvdata(dev); + if (IS_ENABLED(CONFIG_NI_LEGACY_ARM_CACHEINFO_SIZE)) + return sysfs_emit(buf, "%u\n", this_leaf->size); + return sysfs_emit(buf, "%uK\n", this_leaf->size >> 10); }