diff --git a/board/common/uboot/env.dtsi b/board/common/uboot/env.dtsi index f484b51749..750e83114a 100644 --- a/board/common/uboot/env.dtsi +++ b/board/common/uboot/env.dtsi @@ -14,7 +14,6 @@ boot_targets = "virtio mmc"; bootcmd = "run ixboot"; - ixvariant = ""; ixpreboot = /incbin/("scripts/ixpreboot.sh"); ixbtn-devmode = /incbin/("scripts/ixbtn-devmode.sh"); ixbtn-factory = /incbin/("scripts/ixbtn-factory.sh"); diff --git a/board/common/uboot/scripts/ixpreboot.sh b/board/common/uboot/scripts/ixpreboot.sh index 3467f3d051..7b6242e0db 100644 --- a/board/common/uboot/scripts/ixpreboot.sh +++ b/board/common/uboot/scripts/ixpreboot.sh @@ -34,7 +34,7 @@ for tgt in "${boot_targets}"; do if load ${devtype} ${devnum}:${auxpart} ${loadaddr} /uboot.env; then env import -c ${loadaddr} ${filesize} BOOT_ORDER DEBUG ethact BOARD_VARIANT - run ixvariant + test -n "${ixvariant}" && run ixvariant fi if test -n "${DEBUG}"; then diff --git a/board/riscv64/Config.in b/board/riscv64/Config.in index 906f84c44a..9171777c82 100644 --- a/board/riscv64/Config.in +++ b/board/riscv64/Config.in @@ -1,5 +1,6 @@ -if BR2_riscv +if BR2_RISCV_64 -# No boards yet in tree, visionfive2 is not integrated +source "$BR2_EXTERNAL_INFIX_PATH/board/riscv64/bananapi-bpi-f3/Config.in" +source "$BR2_EXTERNAL_INFIX_PATH/board/riscv64/starfive-visionfive2/Config.in" endif diff --git a/board/riscv64/bananapi-bpi-f3/Config.in b/board/riscv64/bananapi-bpi-f3/Config.in new file mode 100644 index 0000000000..2e0460963d --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/Config.in @@ -0,0 +1,6 @@ +config BR2_PACKAGE_BANANAPI_BPI_F3 + bool "Banana Pi BPI-F3" + depends on BR2_RISCV_64 + select SDCARD_AUX + help + Support for the Banana Pi BPI-F3, based on the SpacemiT K1 SoC. diff --git a/board/riscv64/bananapi-bpi-f3/LICENSE b/board/riscv64/bananapi-bpi-f3/LICENSE new file mode 100644 index 0000000000..8cdb30a3aa --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/LICENSE @@ -0,0 +1,13 @@ +Copyright (c) 2026 The KernelKit Authors + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/board/riscv64/bananapi-bpi-f3/README.md b/board/riscv64/bananapi-bpi-f3/README.md new file mode 100644 index 0000000000..2a631648fb --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/README.md @@ -0,0 +1,55 @@ +Banana Pi BPI-F3 +================ + +The [BPI-F3][1] is a SpacemiT K1 (8x RISC-V X60) board with two GbE +ports, eMMC, and a microSD slot. Infix runs from SD card. + +| **Component** | **Source** | +|-----------------|--------------------------------------------------| +| FSBL (DDR init) | SpacemiT `uboot-2022.10`, `k1-bl-v2.2.y` | +| OpenSBI | upstream v1.8.1 | +| U-Boot | `kkit-u-boot-2026.10.y`, `spacemit_k1_defconfig` | + + +How to Build +------------ + +``` +$ make O=x-boot bpi_f3_boot_defconfig +$ make O=x-boot +$ make riscv64_defconfig +$ make +$ ./utils/mkimage.sh -b x-boot -r output bananapi-bpi-f3 +$ sudo dd if=x-boot/images/infix-bpi-f3-sdcard.img of=/dev/mmcblk0 bs=1M status=progress oflag=direct +``` + + +Booting the Board +----------------- + + 1. Connect a 3.3V TTL UART to the debug header, 115200 8N1 + 2. Insert the SD card and power on + + +Limitations +----------- + +Linux 6.18: + + - SD card support needs backported device tree and driver changes + - Reboot and power-off need a backported P1 PMIC driver + - SD card limited to 3.3V signalling (`no-1-8-v`), no UHS modes + - PDMA disabled in the board DT, its probe hangs the boot + - No temperature sensors, the K1 thermal driver landed in v7.2 + - No PCIe, so no WiFi or NVMe, the K1 PCIe drivers landed after 6.18 + - No USB, the K1 USB2 PHY driver landed after 6.18 + - The P1 RTC cannot be read at boot, the clock starts from the build default + +Boot loader: + + - Vendor FSBL (U-Boot 2022.10 SPL) for DDR init + - U-Boot has no Ethernet driver for the K1, so there is no netboot + - U-Boot has no reset driver for the K1, `reset` does nothing + - SD card image only, no eMMC image yet + +[1]: https://docs.banana-pi.org/en/BPI-F3/BananaPi_BPI-F3 diff --git a/board/riscv64/bananapi-bpi-f3/bananapi-bpi-f3.hash b/board/riscv64/bananapi-bpi-f3/bananapi-bpi-f3.hash new file mode 100644 index 0000000000..2b1e744325 --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/bananapi-bpi-f3.hash @@ -0,0 +1,2 @@ +# Locally calculated +sha256 d48246c717b505cc11df95171f2fd548b389e1a463f1af4c68d0b69fe0d1009b LICENSE diff --git a/board/riscv64/bananapi-bpi-f3/bananapi-bpi-f3.mk b/board/riscv64/bananapi-bpi-f3/bananapi-bpi-f3.mk new file mode 100644 index 0000000000..b73a67ba75 --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/bananapi-bpi-f3.mk @@ -0,0 +1,31 @@ +define BANANAPI_BPI_F3_LINUX_CONFIG_FIXUPS + $(call KCONFIG_ENABLE_OPT,CONFIG_ARCH_SPACEMIT) + $(call KCONFIG_ENABLE_OPT,CONFIG_SPACEMIT_CCU) + $(call KCONFIG_ENABLE_OPT,CONFIG_SPACEMIT_K1_CCU) + $(call KCONFIG_ENABLE_OPT,CONFIG_PINCTRL_SPACEMIT_K1) + $(call KCONFIG_ENABLE_OPT,CONFIG_GPIO_SPACEMIT_K1) + $(call KCONFIG_ENABLE_OPT,CONFIG_RESET_SPACEMIT) + $(call KCONFIG_ENABLE_OPT,CONFIG_MFD_SYSCON) + $(call KCONFIG_ENABLE_OPT,CONFIG_SERIAL_8250) + $(call KCONFIG_ENABLE_OPT,CONFIG_SERIAL_8250_CONSOLE) + $(call KCONFIG_ENABLE_OPT,CONFIG_SERIAL_OF_PLATFORM) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMP_PDMA) + $(call KCONFIG_ENABLE_OPT,CONFIG_I2C_K1) + $(call KCONFIG_ENABLE_OPT,CONFIG_MFD_SPACEMIT_P1) + $(call KCONFIG_ENABLE_OPT,CONFIG_REGULATOR_SPACEMIT_P1) + $(call KCONFIG_ENABLE_OPT,CONFIG_REGULATOR_FIXED_VOLTAGE) + $(call KCONFIG_ENABLE_OPT,CONFIG_RTC_DRV_SPACEMIT_P1) + $(call KCONFIG_ENABLE_OPT,CONFIG_POWER_RESET_SPACEMIT_P1) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMC) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMC_SDHCI) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMC_SDHCI_PLTFM) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMC_SDHCI_OF_K1) + $(call KCONFIG_ENABLE_OPT,CONFIG_NET_VENDOR_SPACEMIT) + $(call KCONFIG_ENABLE_OPT,CONFIG_SPACEMIT_K1_EMAC) + $(call KCONFIG_ENABLE_OPT,CONFIG_REALTEK_PHY) + $(call KCONFIG_ENABLE_OPT,CONFIG_LEDS_GPIO) + $(call KCONFIG_ENABLE_OPT,CONFIG_LEDS_TRIGGER_HEARTBEAT) +endef + +$(eval $(ix-board)) +$(eval $(generic-package)) diff --git a/board/riscv64/bananapi-bpi-f3/dts/Makefile b/board/riscv64/bananapi-bpi-f3/dts/Makefile new file mode 100644 index 0000000000..c5f764d39a --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/dts/Makefile @@ -0,0 +1 @@ +dtb-y += spacemit/k1-bananapi-f3.dtb diff --git a/board/riscv64/bananapi-bpi-f3/dts/spacemit/infix.dtsi b/board/riscv64/bananapi-bpi-f3/dts/spacemit/infix.dtsi new file mode 100644 index 0000000000..16cfafc86d --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/dts/spacemit/infix.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common Infix OS defaults + */ + +/ { + chosen { + infix { + /* Default admin user password: 'admin' */ + factory-password-hash = "$5$mI/zpOAqZYKLC2WU$i7iPzZiIjOjrBF3NyftS9CCq8dfYwHwrmUK097Jca9A"; + }; + }; +}; diff --git a/board/riscv64/bananapi-bpi-f3/dts/spacemit/k1-bananapi-f3.dts b/board/riscv64/bananapi-bpi-f3/dts/spacemit/k1-bananapi-f3.dts new file mode 100644 index 0000000000..cb26cbf6ae --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/dts/spacemit/k1-bananapi-f3.dts @@ -0,0 +1,19 @@ +#include +#include "infix.dtsi" + +/* + * UHS needs the pinctrl driver to switch the SD pads' IO power domain + * to 1.8V, which 6.18 does not do. Stay at 3.3V signalling until a + * kernel that does. + */ +&sdhci0 { + no-1-8-v; +}; + +/* + * The 6.18 PDMA driver hangs the boot in probe on this board, and no + * peripheral uses DMA yet. + */ +&pdma { + status = "disabled"; +}; diff --git a/board/riscv64/bananapi-bpi-f3/genimage.cfg.in b/board/riscv64/bananapi-bpi-f3/genimage.cfg.in new file mode 100644 index 0000000000..37d1eec092 --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/genimage.cfg.in @@ -0,0 +1,92 @@ +image cfg.ext4 { + empty = true + temporary = true + size = 16M + + ext4 { + label = "cfg" + use-mke2fs = true + features = "uninit_bg" + extraargs = "-m 0 -i 4096" + } +} + +# The /var partition will be expanded automatically at first boot +# to use the full size of the SD-card or eMMC media. +image var.ext4 { + empty = true + temporary = true + size = 128M + + ext4 { + label = "var" + use-mke2fs = true + features = "uninit_bg" + extraargs = "-m 0 -i 4096" + } +} + +image #IX_ID##VERSION#-bpi-f3-sdcard.img { + hdimage { + partition-table-type = "gpt" + } + + partition bootinfo { + in-partition-table = false + offset = 0 + image = "bootinfo_sd.bin" + } + + partition fsbl { + offset = 128K + size = 256K + image = "FSBL.bin" + } + + # Read by the vendor FSBL, left empty for its built-in defaults + partition env { + offset = 384K + size = 64K + } + + partition opensbi { + offset = 1M + size = 1M + image = "fw_dynamic.itb" + } + + partition uboot { + offset = 2M + size = 2M + image = "u-boot.itb" + } + + partition aux { + partition-uuid = D4EF35A0-0652-45A1-B3DE-D63339C82035 + image = "aux.ext4" + } + + partition primary { + partition-type-uuid = linux + bootable = true + size = 250M + image = "rootfs.squashfs" + } + + partition secondary { + partition-type-uuid = linux + bootable = true + size = 250M + image = "rootfs.squashfs" + } + + partition cfg { + partition-uuid = 7aa497f0-73b5-47e5-b2ab-8752d8a48105 + image = "cfg.ext4" + } + + partition var { + partition-uuid = 8046A06A-E45A-4A14-A6AD-6684704A393F + image = "var.ext4" + } +} diff --git a/board/riscv64/bananapi-bpi-f3/rootfs/usr/share/product/bananapi,bpi-f3/etc/factory-config.cfg b/board/riscv64/bananapi-bpi-f3/rootfs/usr/share/product/bananapi,bpi-f3/etc/factory-config.cfg new file mode 100644 index 0000000000..4ed8641535 --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/rootfs/usr/share/product/bananapi,bpi-f3/etc/factory-config.cfg @@ -0,0 +1,363 @@ +{ + "ieee802-dot1ab-lldp:lldp": { + "infix-lldp:enabled": true + }, + "ietf-hardware:hardware": { + "component": [ + { + "class": "infix-hardware:usb", + "name": "USB", + "state": { + "admin-state": "unlocked" + } + } + ] + }, + "ietf-interfaces:interfaces": { + "interface": [ + { + "name": "eth0", + "type": "infix-if-type:ethernet", + "ietf-ip:ipv4": { + "infix-dhcp-client:dhcp": { + "option": [ + { + "id": "ntp-server" + }, + { + "id": "broadcast" + }, + { + "id": "domain" + }, + { + "id": "hostname", + "value": "auto" + }, + { + "id": "dns-server" + }, + { + "id": "router" + }, + { + "id": "netmask" + }, + { + "id": "vendor-class", + "value": "Banana Pi BPI-F3" + } + ] + } + }, + "ietf-ip:ipv6": { + "infix-dhcpv6-client:dhcp": { + "option": [ + { + "id": "ntp-server" + }, + { + "id": "client-fqdn" + }, + { + "id": "domain-search" + }, + { + "id": "dns-server" + } + ] + } + } + }, + { + "name": "eth1", + "type": "infix-if-type:ethernet", + "ietf-ip:ipv4": { + "infix-dhcp-client:dhcp": { + "option": [ + { + "id": "ntp-server" + }, + { + "id": "broadcast" + }, + { + "id": "domain" + }, + { + "id": "hostname", + "value": "auto" + }, + { + "id": "dns-server" + }, + { + "id": "router" + }, + { + "id": "netmask" + }, + { + "id": "vendor-class", + "value": "Banana Pi BPI-F3" + } + ] + } + }, + "ietf-ip:ipv6": { + "infix-dhcpv6-client:dhcp": { + "option": [ + { + "id": "ntp-server" + }, + { + "id": "client-fqdn" + }, + { + "id": "domain-search" + }, + { + "id": "dns-server" + } + ] + } + } + }, + { + "name": "lo", + "type": "infix-if-type:loopback", + "ietf-ip:ipv4": { + "address": [ + { + "ip": "127.0.0.1", + "prefix-length": 8 + } + ] + }, + "ietf-ip:ipv6": { + "address": [ + { + "ip": "::1", + "prefix-length": 128 + } + ] + } + } + ] + }, + "ietf-keystore:keystore": { + "asymmetric-keys": { + "asymmetric-key": [ + { + "name": "gencert", + "public-key-format": "infix-crypto-types:x509-public-key-format", + "public-key": "", + "private-key-format": "infix-crypto-types:rsa-private-key-format", + "cleartext-private-key": "", + "certificates": {} + }, + { + "name": "genkey", + "public-key-format": "infix-crypto-types:ssh-public-key-format", + "public-key": "", + "private-key-format": "infix-crypto-types:rsa-private-key-format", + "cleartext-private-key": "", + "certificates": {} + } + ] + } + }, + "ietf-netconf-acm:nacm": { + "enable-nacm": true, + "read-default": "permit", + "write-default": "permit", + "exec-default": "permit", + "groups": { + "group": [ + { + "name": "admin", + "user-name": [ + "admin" + ] + }, + { + "name": "operator", + "user-name": [] + }, + { + "name": "guest", + "user-name": [] + } + ] + }, + "rule-list": [ + { + "name": "admin-acl", + "group": [ + "admin" + ], + "rule": [ + { + "name": "permit-all", + "module-name": "*", + "access-operations": "*", + "action": "permit", + "comment": "Allow 'admin' group complete access to all operations and data." + } + ] + }, + { + "name": "operator-acl", + "group": [ + "operator" + ], + "rule": [ + { + "name": "permit-system-rpcs", + "module-name": "ietf-system", + "rpc-name": "*", + "access-operations": "exec", + "action": "permit", + "comment": "Operators can reboot, shutdown, and set system time." + } + ] + }, + { + "name": "guest-acl", + "group": [ + "guest" + ], + "rule": [ + { + "name": "deny-all-write+exec", + "module-name": "*", + "access-operations": "create update delete exec", + "action": "deny", + "comment": "Guests cannot change anything or exec rpcs." + } + ] + }, + { + "name": "default-deny-all", + "group": [ + "*" + ], + "rule": [ + { + "name": "deny-password-access", + "path": "/ietf-system:system/authentication/user/password", + "access-operations": "*", + "action": "deny", + "comment": "No user except admins can access password hashes." + }, + { + "name": "deny-keystore-access", + "module-name": "ietf-keystore", + "access-operations": "*", + "action": "deny", + "comment": "No user except admins can access cryptographic keys." + }, + { + "name": "deny-truststore-access", + "module-name": "ietf-truststore", + "access-operations": "*", + "action": "deny", + "comment": "No user except admins can access trust store." + } + ] + } + ] + }, + "ietf-system:system": { + "hostname": "bpi-f3-%m", + "infix-system:software": { + "update-url": "https://github.com/kernelkit/infix/releases.atom" + }, + "infix-schedule:schedules": { + "schedule": [ + { + "name": "nightly", + "description": "Every night at 03:00", + "recurrence": { + "frequency": "ietf-schedule:daily", + "byhour": [ + 3 + ] + } + }, + { + "name": "weekly", + "description": "Sunday nights at 03:00", + "recurrence": { + "frequency": "ietf-schedule:weekly", + "byday": [ + { + "weekday": "sunday" + } + ], + "byhour": [ + 3 + ] + } + } + ] + }, + "ntp": { + "server": [ + { + "name": "default", + "udp": { + "address": "pool.ntp.org" + } + } + ] + }, + "authentication": { + "user": [ + { + "name": "admin", + "password": "$factory$", + "infix-system:shell": "bash" + } + ] + }, + "infix-system:motd-banner": "Li0tLS0tLS0uCnwgIC4gLiAgfCBJbmZpeCBPUyDigJQgSW1tdXRhYmxlLkZyaWVuZGx5LlNlY3VyZQp8LS4gdiAuLXwgaHR0cHM6Ly9rZXJuZWxraXQub3JnCictJy0tLSctJwo=" + }, + "infix-meta:meta": { + "version": "1.11" + }, + "infix-services:mdns": { + "enabled": true + }, + "infix-services:ssh": { + "enabled": true, + "hostkey": [ + "genkey" + ], + "listen": [ + { + "name": "ipv4", + "address": "0.0.0.0", + "port": 22 + }, + { + "name": "ipv6", + "address": "::", + "port": 22 + } + ] + }, + "infix-services:web": { + "enabled": true, + "certificate": "gencert", + "console": { + "enabled": true + }, + "netbrowse": { + "enabled": true + }, + "restconf": { + "enabled": true + } + } +} diff --git a/board/riscv64/bananapi-bpi-f3/rootfs/usr/share/product/bananapi,bpi-f3/etc/product/interface-quirks.json b/board/riscv64/bananapi-bpi-f3/rootfs/usr/share/product/bananapi,bpi-f3/etc/product/interface-quirks.json new file mode 100644 index 0000000000..144429a0f2 --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/rootfs/usr/share/product/bananapi,bpi-f3/etc/product/interface-quirks.json @@ -0,0 +1,6 @@ +{ + "@ethtool:driver=k1_emac": { + "comment": "The PHY is only attached while the interface is up", + "phy-detached-when-down": true + } +} diff --git a/board/riscv64/bananapi-bpi-f3/uboot/bpi-f3-env.dtsi b/board/riscv64/bananapi-bpi-f3/uboot/bpi-f3-env.dtsi new file mode 100644 index 0000000000..d513aa9529 --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/uboot/bpi-f3-env.dtsi @@ -0,0 +1,21 @@ +/ { + config { + environment { + boot_targets = "mmc1"; + fdtfile = "spacemit/k1-bananapi-f3.dtb"; + + /* The K1 board code sets no load addresses. DRAM + * starts at 0, keep it all in the first GiB with + * the squashfs, loaded whole, last */ + kernel_addr_r = "0x10000000"; + fdt_addr_r = "0x14000000"; + scriptaddr = "0x14100000"; + pxefile_addr_r = "0x14200000"; + ramdisk_addr_r = "0x20000000"; + + /* This is a development platform, hard code developer mode */ + ixbtn-devmode = "setenv dev_mode yes; echo Enabled"; + ixbtn-factory = "echo \"No button available, use bootmenu\""; + }; + }; +}; diff --git a/board/riscv64/bananapi-bpi-f3/uboot/extras.config b/board/riscv64/bananapi-bpi-f3/uboot/extras.config new file mode 100644 index 0000000000..d1f7ce2c4b --- /dev/null +++ b/board/riscv64/bananapi-bpi-f3/uboot/extras.config @@ -0,0 +1,6 @@ +CONFIG_DEVICE_TREE_INCLUDES="infix-env.dtsi infix-key.dtsi bpi-f3-env.dtsi" +CONFIG_SYS_PROMPT="(bpi-f3) " + +CONFIG_ENV_IS_NOWHERE=y +# CONFIG_ENV_IS_IN_MMC is not set +# CONFIG_TOOLS_MKEFICAPSULE is not set diff --git a/board/riscv64/linux_defconfig b/board/riscv64/linux_defconfig index 05f3b4922e..1e88a6590f 100644 --- a/board/riscv64/linux_defconfig +++ b/board/riscv64/linux_defconfig @@ -1,6 +1,5 @@ CONFIG_SYSVIPC=y CONFIG_POSIX_MQUEUE=y -# CONFIG_CROSS_MEMORY_ATTACH is not set CONFIG_AUDIT=y CONFIG_NO_HZ_IDLE=y CONFIG_HIGH_RES_TIMERS=y @@ -13,8 +12,6 @@ CONFIG_TASKSTATS=y CONFIG_TASK_DELAY_ACCT=y CONFIG_TASK_XACCT=y CONFIG_TASK_IO_ACCOUNTING=y -CONFIG_PSI=y -# CONFIG_CPU_ISOLATION is not set CONFIG_IKCONFIG=y CONFIG_IKCONFIG_PROC=y CONFIG_LOG_BUF_SHIFT=18 @@ -29,50 +26,29 @@ CONFIG_CGROUP_DEVICE=y CONFIG_CGROUP_CPUACCT=y CONFIG_CGROUP_PERF=y CONFIG_CGROUP_BPF=y -CONFIG_NAMESPACES=y CONFIG_USER_NS=y CONFIG_SCHED_AUTOGROUP=y CONFIG_BLK_DEV_INITRD=y -# CONFIG_RD_BZIP2 is not set -# CONFIG_RD_LZMA is not set -# CONFIG_RD_XZ is not set -# CONFIG_RD_LZO is not set -# CONFIG_RD_LZ4 is not set -CONFIG_EXPERT=y -# CONFIG_SYSFS_SYSCALL is not set CONFIG_KALLSYMS_ALL=y CONFIG_PROFILING=y -CONFIG_SOC_STARFIVE=y -CONFIG_ERRATA_SIFIVE=y -CONFIG_NONPORTABLE=y CONFIG_SMP=y -# CONFIG_RISCV_ISA_SVPBMT is not set -# CONFIG_COMPAT is not set -CONFIG_HIBERNATION=y +# CONFIG_SUSPEND is not set +CONFIG_PM=y CONFIG_CPU_IDLE=y CONFIG_RISCV_SBI_CPUIDLE=y CONFIG_CPU_FREQ=y -CONFIG_CPU_FREQ_GOV_POWERSAVE=y -CONFIG_CPU_FREQ_GOV_USERSPACE=y -CONFIG_CPU_FREQ_GOV_CONSERVATIVE=y CONFIG_CPU_FREQ_GOV_SCHEDUTIL=y CONFIG_CPUFREQ_DT=y CONFIG_KPROBES=y -CONFIG_JUMP_LABEL=y -# CONFIG_STACKPROTECTOR is not set -# CONFIG_GCC_PLUGINS is not set CONFIG_MODULES=y CONFIG_MODULE_UNLOAD=y -CONFIG_MODULE_COMPRESS_ZSTD=y -# CONFIG_BLOCK_LEGACY_AUTOLOAD is not set -CONFIG_BLK_WBT=y -# CONFIG_BLK_DEBUG_FS is not set CONFIG_PARTITION_ADVANCED=y -# CONFIG_MQ_IOSCHED_DEADLINE is not set -# CONFIG_MQ_IOSCHED_KYBER is not set +# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set +# CONFIG_COMPAT_BRK is not set CONFIG_KSM=y CONFIG_TRANSPARENT_HUGEPAGE=y CONFIG_CMA=y +CONFIG_CMA_AREAS=7 CONFIG_NET=y CONFIG_PACKET=y CONFIG_XDP_SOCKETS=y @@ -81,7 +57,6 @@ CONFIG_IP_MULTICAST=y CONFIG_IP_ADVANCED_ROUTER=y CONFIG_IP_MULTIPLE_TABLES=y CONFIG_IP_ROUTE_MULTIPATH=y -CONFIG_IP_PNP=y CONFIG_NET_IPIP=m CONFIG_NET_IPGRE_DEMUX=m CONFIG_NET_IPGRE=m @@ -90,11 +65,9 @@ CONFIG_IP_MROUTE=y CONFIG_IP_MROUTE_MULTIPLE_TABLES=y CONFIG_IP_PIMSM_V1=y CONFIG_IP_PIMSM_V2=y -CONFIG_SYN_COOKIES=y CONFIG_NET_IPVTI=m CONFIG_NET_FOU_IP_TUNNELS=y -CONFIG_INET_DIAG=m -# CONFIG_IPV6_SIT is not set +CONFIG_IPV6_SIT=m CONFIG_IPV6_GRE=m CONFIG_IPV6_MULTIPLE_TABLES=y CONFIG_IPV6_SUBTREES=y @@ -107,12 +80,31 @@ CONFIG_BRIDGE_NETFILTER=y CONFIG_NETFILTER_NETLINK_QUEUE=y CONFIG_NETFILTER_NETLINK_LOG=y CONFIG_NF_CONNTRACK=y +CONFIG_NF_CONNTRACK_ZONES=y +CONFIG_NF_CONNTRACK_PROCFS=y CONFIG_NF_CONNTRACK_EVENTS=y +CONFIG_NF_CONNTRACK_TIMEOUT=y +CONFIG_NF_CONNTRACK_TIMESTAMP=y +CONFIG_NF_CONNTRACK_AMANDA=y CONFIG_NF_CONNTRACK_FTP=y +CONFIG_NF_CONNTRACK_H323=y +CONFIG_NF_CONNTRACK_IRC=y +CONFIG_NF_CONNTRACK_NETBIOS_NS=y +CONFIG_NF_CONNTRACK_SNMP=y +CONFIG_NF_CONNTRACK_PPTP=y +CONFIG_NF_CONNTRACK_SANE=y +CONFIG_NF_CONNTRACK_SIP=y +CONFIG_NF_CONNTRACK_TFTP=y +CONFIG_NF_CT_NETLINK=y +CONFIG_NF_CT_NETLINK_TIMEOUT=y +CONFIG_NF_CT_NETLINK_HELPER=y +CONFIG_NETFILTER_NETLINK_GLUE_CT=y CONFIG_NF_TABLES=y CONFIG_NF_TABLES_INET=y CONFIG_NF_TABLES_NETDEV=y +CONFIG_NFT_NUMGEN=y CONFIG_NFT_CT=m +CONFIG_NFT_FLOW_OFFLOAD=y CONFIG_NFT_CONNLIMIT=m CONFIG_NFT_LOG=m CONFIG_NFT_LIMIT=m @@ -121,15 +113,23 @@ CONFIG_NFT_REDIR=m CONFIG_NFT_NAT=m CONFIG_NFT_TUNNEL=m CONFIG_NFT_QUEUE=m +CONFIG_NFT_QUOTA=y CONFIG_NFT_REJECT=m CONFIG_NFT_COMPAT=m CONFIG_NFT_HASH=m +CONFIG_NFT_FIB_INET=y CONFIG_NFT_XFRM=m CONFIG_NFT_SOCKET=m CONFIG_NFT_OSF=m +CONFIG_NFT_TPROXY=y +CONFIG_NFT_SYNPROXY=y CONFIG_NFT_DUP_NETDEV=m CONFIG_NFT_FWD_NETDEV=m +CONFIG_NFT_FIB_NETDEV=y CONFIG_NFT_REJECT_NETDEV=m +CONFIG_NF_FLOW_TABLE_INET=y +CONFIG_NF_FLOW_TABLE=y +CONFIG_NETFILTER_XTABLES_LEGACY=y CONFIG_NETFILTER_XT_TARGET_CHECKSUM=m CONFIG_NETFILTER_XT_TARGET_LOG=m CONFIG_NETFILTER_XT_MATCH_ADDRTYPE=m @@ -146,29 +146,69 @@ CONFIG_NETFILTER_XT_MATCH_MAC=m CONFIG_NETFILTER_XT_MATCH_MARK=m CONFIG_NETFILTER_XT_MATCH_MULTIPORT=m CONFIG_NETFILTER_XT_MATCH_PHYSDEV=m +CONFIG_IP_SET=y +CONFIG_IP_SET_BITMAP_IP=y +CONFIG_IP_SET_BITMAP_IPMAC=y +CONFIG_IP_SET_BITMAP_PORT=y +CONFIG_IP_SET_HASH_IP=y +CONFIG_IP_SET_HASH_IPMARK=y +CONFIG_IP_SET_HASH_IPPORT=y +CONFIG_IP_SET_HASH_IPPORTIP=y +CONFIG_IP_SET_HASH_IPPORTNET=y +CONFIG_IP_SET_HASH_IPMAC=y +CONFIG_IP_SET_HASH_MAC=y +CONFIG_IP_SET_HASH_NETPORTNET=y +CONFIG_IP_SET_HASH_NET=y +CONFIG_IP_SET_HASH_NETNET=y +CONFIG_IP_SET_HASH_NETPORT=y +CONFIG_IP_SET_HASH_NETIFACE=y +CONFIG_IP_SET_LIST_SET=y +CONFIG_NFT_DUP_IPV4=y +CONFIG_NFT_FIB_IPV4=y +CONFIG_NF_TABLES_ARP=y +CONFIG_NF_LOG_ARP=y +CONFIG_NF_LOG_IPV4=y CONFIG_IP_NF_IPTABLES=m -CONFIG_IP_NF_FILTER=m +CONFIG_IP_NF_MATCH_AH=m +CONFIG_IP_NF_MATCH_ECN=m +CONFIG_IP_NF_MATCH_RPFILTER=m +CONFIG_IP_NF_MATCH_TTL=m CONFIG_IP_NF_TARGET_REJECT=m +CONFIG_IP_NF_TARGET_SYNPROXY=m CONFIG_IP_NF_NAT=m CONFIG_IP_NF_TARGET_MASQUERADE=m -CONFIG_IP_NF_MANGLE=m +CONFIG_IP_NF_TARGET_NETMAP=m +CONFIG_IP_NF_TARGET_REDIRECT=m +CONFIG_IP_NF_TARGET_ECN=m +CONFIG_IP_NF_TARGET_TTL=m +CONFIG_IP_NF_RAW=m +CONFIG_IP_NF_ARPFILTER=m +CONFIG_IP_NF_ARP_MANGLE=m +CONFIG_NFT_DUP_IPV6=y +CONFIG_NFT_FIB_IPV6=y CONFIG_IP6_NF_IPTABLES=m CONFIG_IP6_NF_MATCH_AH=m CONFIG_IP6_NF_MATCH_EUI64=m +CONFIG_IP6_NF_MATCH_FRAG=m +CONFIG_IP6_NF_MATCH_OPTS=m +CONFIG_IP6_NF_MATCH_HL=m CONFIG_IP6_NF_MATCH_IPV6HEADER=m -CONFIG_IP6_NF_FILTER=m +CONFIG_IP6_NF_MATCH_MH=m +CONFIG_IP6_NF_MATCH_RPFILTER=m +CONFIG_IP6_NF_MATCH_RT=m +CONFIG_IP6_NF_MATCH_SRH=m +CONFIG_IP6_NF_TARGET_HL=m CONFIG_IP6_NF_TARGET_REJECT=m +CONFIG_IP6_NF_TARGET_SYNPROXY=m CONFIG_IP6_NF_RAW=m CONFIG_IP6_NF_NAT=m CONFIG_IP6_NF_TARGET_MASQUERADE=m CONFIG_IP6_NF_TARGET_NPT=m CONFIG_NF_TABLES_BRIDGE=m CONFIG_NFT_BRIDGE_META=m +CONFIG_NFT_BRIDGE_REJECT=m CONFIG_NF_CONNTRACK_BRIDGE=m CONFIG_BRIDGE_NF_EBTABLES=m -CONFIG_BRIDGE_EBT_BROUTE=m -CONFIG_BRIDGE_EBT_T_FILTER=m -CONFIG_BRIDGE_EBT_T_NAT=m CONFIG_BRIDGE_EBT_802_3=m CONFIG_BRIDGE_EBT_ARP=m CONFIG_BRIDGE_EBT_IP=m @@ -211,7 +251,6 @@ CONFIG_NET_PKTGEN=y CONFIG_NET_9P=y CONFIG_NET_9P_VIRTIO=y CONFIG_LWTUNNEL=y -# CONFIG_ETHTOOL_NETLINK is not set CONFIG_PCI=y CONFIG_PCIEPORTBUS=y CONFIG_PCI_IOV=y @@ -220,13 +259,8 @@ CONFIG_UEVENT_HELPER=y CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" CONFIG_DEVTMPFS=y CONFIG_DEVTMPFS_MOUNT=y -# CONFIG_STANDALONE is not set -# CONFIG_PREVENT_FIRMWARE_BUILD is not set -CONFIG_FW_LOADER=m -CONFIG_SIFIVE_CCACHE=y CONFIG_FW_CFG_SYSFS=y CONFIG_FW_CFG_SYSFS_CMDLINE=y -CONFIG_EFI_DISABLE_RUNTIME=y CONFIG_MTD=y CONFIG_MTD_BLOCK=y CONFIG_MTD_BLOCK2MTD=y @@ -234,20 +268,20 @@ CONFIG_MTD_RAW_NAND=y CONFIG_MTD_SPI_NOR=y CONFIG_OF_OVERLAY=y CONFIG_BLK_DEV_NULL_BLK=y -CONFIG_ZRAM=y -CONFIG_ZRAM_MEMORY_TRACKING=y CONFIG_BLK_DEV_LOOP=y -CONFIG_BLK_DEV_LOOP_MIN_COUNT=1 CONFIG_BLK_DEV_RAM=y CONFIG_VIRTIO_BLK=y CONFIG_BLK_DEV_NVME=y +CONFIG_SRAM=y CONFIG_EEPROM_AT24=y +# CONFIG_SCSI_PROC_FS is not set CONFIG_BLK_DEV_SD=y CONFIG_SCSI_SAS_LIBSAS=y CONFIG_SCSI_SAS_ATA=y CONFIG_SCSI_VIRTIO=y CONFIG_ATA=y CONFIG_SATA_AHCI=y +CONFIG_SATA_MOBILE_LPM_POLICY=0 CONFIG_SATA_AHCI_PLATFORM=y CONFIG_PATA_OF_PLATFORM=y CONFIG_MD=y @@ -258,6 +292,7 @@ CONFIG_DM_VERITY_VERIFY_ROOTHASH_SIG=y CONFIG_NETDEVICES=y CONFIG_BONDING=m CONFIG_DUMMY=m +CONFIG_WIREGUARD=m CONFIG_MACVLAN=m CONFIG_MACVTAP=m CONFIG_IPVLAN=m @@ -271,13 +306,66 @@ CONFIG_VETH=m CONFIG_VIRTIO_NET=y CONFIG_NLMON=y CONFIG_NET_VRF=y +# CONFIG_NET_VENDOR_3COM is not set +# CONFIG_NET_VENDOR_ADAPTEC is not set +# CONFIG_NET_VENDOR_AGERE is not set +# CONFIG_NET_VENDOR_ALACRITECH is not set +# CONFIG_NET_VENDOR_ALTEON is not set +# CONFIG_NET_VENDOR_AMAZON is not set +# CONFIG_NET_VENDOR_AMD is not set +# CONFIG_NET_VENDOR_AQUANTIA is not set +# CONFIG_NET_VENDOR_ARC is not set +# CONFIG_NET_VENDOR_ATHEROS is not set +# CONFIG_NET_VENDOR_BROADCOM is not set +# CONFIG_NET_VENDOR_CADENCE is not set +# CONFIG_NET_VENDOR_CAVIUM is not set +# CONFIG_NET_VENDOR_CHELSIO is not set +# CONFIG_NET_VENDOR_CISCO is not set +# CONFIG_NET_VENDOR_CORTINA is not set +# CONFIG_NET_VENDOR_DEC is not set +# CONFIG_NET_VENDOR_DLINK is not set +# CONFIG_NET_VENDOR_EMULEX is not set +# CONFIG_NET_VENDOR_EZCHIP is not set +# CONFIG_NET_VENDOR_GOOGLE is not set +# CONFIG_NET_VENDOR_HISILICON is not set +# CONFIG_NET_VENDOR_HUAWEI is not set +# CONFIG_NET_VENDOR_MELLANOX is not set +# CONFIG_NET_VENDOR_META is not set +# CONFIG_NET_VENDOR_MICREL is not set +# CONFIG_NET_VENDOR_MICROSEMI is not set +# CONFIG_NET_VENDOR_MYRI is not set +# CONFIG_NET_VENDOR_NI is not set +# CONFIG_NET_VENDOR_NATSEMI is not set +# CONFIG_NET_VENDOR_NETERION is not set +# CONFIG_NET_VENDOR_NETRONOME is not set +# CONFIG_NET_VENDOR_NVIDIA is not set +# CONFIG_NET_VENDOR_OKI is not set +# CONFIG_NET_VENDOR_PACKET_ENGINES is not set +# CONFIG_NET_VENDOR_PENSANDO is not set +# CONFIG_NET_VENDOR_QLOGIC is not set +# CONFIG_NET_VENDOR_BROCADE is not set +# CONFIG_NET_VENDOR_QUALCOMM is not set +# CONFIG_NET_VENDOR_RDC is not set CONFIG_8139CP=y -CONFIG_STMMAC_ETH=y -CONFIG_DWMAC_DWC_QOS_ETH=y -# CONFIG_DWMAC_GENERIC is not set -CONFIG_DWMAC_STARFIVE=y +# CONFIG_NET_VENDOR_RENESAS is not set +# CONFIG_NET_VENDOR_ROCKER is not set +# CONFIG_NET_VENDOR_SAMSUNG is not set +# CONFIG_NET_VENDOR_SEEQ is not set +# CONFIG_NET_VENDOR_SILAN is not set +# CONFIG_NET_VENDOR_SIS is not set +# CONFIG_NET_VENDOR_SOLARFLARE is not set +# CONFIG_NET_VENDOR_SMSC is not set +# CONFIG_NET_VENDOR_SOCIONEXT is not set +# CONFIG_NET_VENDOR_STMICRO is not set +# CONFIG_NET_VENDOR_SUN is not set +# CONFIG_NET_VENDOR_SYNOPSYS is not set +# CONFIG_NET_VENDOR_TEHUTI is not set +# CONFIG_NET_VENDOR_TI is not set +# CONFIG_NET_VENDOR_VIA is not set +# CONFIG_NET_VENDOR_WIZNET is not set +# CONFIG_NET_VENDOR_XILINX is not set +CONFIG_SFP=y CONFIG_MICROCHIP_PHY=y -CONFIG_MOTORCOMM_PHY=y CONFIG_PPP=m CONFIG_PPPOE=m CONFIG_USB_RTL8150=m @@ -290,7 +378,6 @@ CONFIG_USB_NET_DM9601=m CONFIG_USB_NET_SMSC75XX=m CONFIG_USB_NET_SMSC95XX=m # CONFIG_USB_NET_NET1080 is not set -# CONFIG_USB_NET_CDC_SUBSET is not set CONFIG_USB_ALI_M5632=y CONFIG_USB_AN2720=y CONFIG_USB_EPSON2888=y @@ -300,90 +387,73 @@ CONFIG_USB_KC2190=y CONFIG_INPUT_EVDEV=y CONFIG_KEYBOARD_GPIO=y # CONFIG_INPUT_MOUSE is not set -# CONFIG_VT is not set +# CONFIG_SERIO_SERPORT is not set +CONFIG_VT_HW_CONSOLE_BINDING=y # CONFIG_LEGACY_PTYS is not set -# CONFIG_LDISC_AUTOLOAD is not set CONFIG_SERIAL_8250=y -# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set -# CONFIG_SERIAL_8250_16550A_VARIANTS is not set CONFIG_SERIAL_8250_CONSOLE=y -CONFIG_SERIAL_8250_NR_UARTS=6 -CONFIG_SERIAL_8250_RUNTIME_UARTS=6 -CONFIG_SERIAL_8250_EXTENDED=y -CONFIG_SERIAL_8250_MANY_PORTS=y -CONFIG_SERIAL_8250_DW=y CONFIG_SERIAL_OF_PLATFORM=y +CONFIG_SERIAL_EARLYCON_RISCV_SBI=y CONFIG_VIRTIO_CONSOLE=y -CONFIG_HW_RANDOM=y -CONFIG_HW_RANDOM_JH7110=y -# CONFIG_I2C_COMPAT is not set +CONFIG_I2C=y CONFIG_I2C_CHARDEV=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_GPIO=y CONFIG_I2C_MUX_PCA954x=y CONFIG_I2C_MUX_PINCTRL=y -CONFIG_I2C_DESIGNWARE_PLATFORM=y CONFIG_I2C_SLAVE=y CONFIG_SPI=y -CONFIG_SPI_CADENCE_QUADSPI=y -CONFIG_SPI_PL022=y -CONFIG_SPI_SPIDEV=y -# CONFIG_PTP_1588_CLOCK is not set -CONFIG_GPIOLIB_FASTPATH_LIMIT=128 -CONFIG_GPIO_SYSFS=y +CONFIG_SPI_MUX=y +CONFIG_SPI_SPIDEV=m +CONFIG_PINCTRL=y +CONFIG_GPIOLIB=y +CONFIG_GPIO_PCA953X=y +CONFIG_GPIO_PCA953X_IRQ=y +CONFIG_GPIO_PCF857X=y CONFIG_POWER_RESET=y CONFIG_POWER_RESET_GPIO_RESTART=y -CONFIG_SENSORS_SFCTEMP=y +CONFIG_POWER_RESET_SYSCON=y +CONFIG_SENSORS_JC42=y +CONFIG_SENSORS_LM90=m +CONFIG_SENSORS_INA2XX=m CONFIG_THERMAL=y CONFIG_CPU_THERMAL=y CONFIG_THERMAL_EMULATION=y CONFIG_WATCHDOG=y CONFIG_WATCHDOG_SYSFS=y CONFIG_SOFT_WATCHDOG=y -CONFIG_MFD_AXP20X_I2C=y +CONFIG_GPIO_WATCHDOG=y CONFIG_REGULATOR=y CONFIG_REGULATOR_FIXED_VOLTAGE=y -CONFIG_REGULATOR_AXP20X=y -CONFIG_MEDIA_SUPPORT=y -CONFIG_V4L_PLATFORM_DRIVERS=y -CONFIG_VIDEO_CADENCE_CSI2RX=y -CONFIG_VIDEO_IMX219=y -CONFIG_DRM=y -CONFIG_BACKLIGHT_CLASS_DEVICE=y -CONFIG_SOUND=y -CONFIG_SND=y -CONFIG_SND_SOC=y -CONFIG_SND_DESIGNWARE_I2S=y -CONFIG_SND_SOC_STARFIVE=y -CONFIG_SND_SOC_JH7110_PWMDAC=y -CONFIG_SND_SOC_JH7110_TDM=y -CONFIG_SND_SOC_WM8960=y -CONFIG_SND_SIMPLE_CARD=y +CONFIG_REGULATOR_GPIO=y +# CONFIG_HID_GENERIC is not set +# CONFIG_HID_A4TECH is not set +# CONFIG_HID_APPLE is not set +# CONFIG_HID_BELKIN is not set +# CONFIG_HID_CHERRY is not set +# CONFIG_HID_CHICONY is not set +# CONFIG_HID_CYPRESS is not set +# CONFIG_HID_EZKEY is not set +# CONFIG_HID_KENSINGTON is not set +# CONFIG_HID_MICROSOFT is not set +# CONFIG_HID_MONTEREY is not set CONFIG_USB=y CONFIG_USB_ANNOUNCE_NEW_DEVICES=y -CONFIG_USB_XHCI_HCD=y -CONFIG_USB_EHCI_HCD=y -CONFIG_USB_EHCI_HCD_PLATFORM=y -CONFIG_USB_OHCI_HCD=y -CONFIG_USB_OHCI_HCD_PLATFORM=y -CONFIG_USB_STORAGE=y -CONFIG_USB_UAS=y -CONFIG_USB_CDNS_SUPPORT=y -CONFIG_USB_CDNS3=y -CONFIG_USB_CDNS3_GADGET=y -CONFIG_USB_CDNS3_HOST=y -CONFIG_USB_CDNS3_STARFIVE=y +CONFIG_USB_OTG=y +CONFIG_USB_XHCI_HCD=m +CONFIG_USB_EHCI_HCD=m +CONFIG_USB_EHCI_ROOT_HUB_TT=y +CONFIG_USB_EHCI_HCD_PLATFORM=m +CONFIG_USB_OHCI_HCD=m +CONFIG_USB_OHCI_HCD_PLATFORM=m +CONFIG_USB_STORAGE=m CONFIG_USB_GADGET=y -CONFIG_USB_CONFIGFS=y -CONFIG_USB_CONFIGFS_F_FS=y CONFIG_MMC=y -# CONFIG_PWRSEQ_EMMC is not set -# CONFIG_PWRSEQ_SIMPLE is not set +CONFIG_MMC_BLOCK_MINORS=32 CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_PCI=y CONFIG_MMC_SDHCI_PLTFM=y -CONFIG_MMC_SDHCI_OF_DWCMSHC=y -CONFIG_MMC_DW=y -CONFIG_MMC_DW_STARFIVE=y +CONFIG_MMC_SPI=y CONFIG_NEW_LEDS=y CONFIG_LEDS_CLASS=y CONFIG_LEDS_GPIO=y @@ -397,59 +467,36 @@ CONFIG_RTC_CLASS=y CONFIG_RTC_DRV_PCF8523=y CONFIG_RTC_DRV_DS3232=y CONFIG_RTC_DRV_EFI=y -CONFIG_RTC_DRV_PL031=y CONFIG_DMADEVICES=y -CONFIG_AMBA_PL08X=y -CONFIG_DW_AXI_DMAC=y -CONFIG_DMATEST=y -# CONFIG_VIRTIO_MENU is not set -# CONFIG_VHOST_MENU is not set -CONFIG_STAGING=y -CONFIG_STAGING_MEDIA=y -CONFIG_VIDEO_STARFIVE_CAMSS=y -CONFIG_CLK_STARFIVE_JH7110_AON=y -CONFIG_CLK_STARFIVE_JH7110_STG=y -CONFIG_CLK_STARFIVE_JH7110_ISP=y -CONFIG_CLK_STARFIVE_JH7110_VOUT=y -# CONFIG_IOMMU_SUPPORT is not set +CONFIG_VIRTIO_PCI=y +CONFIG_VIRTIO_BALLOON=y +CONFIG_VIRTIO_INPUT=y +CONFIG_VIRTIO_MMIO=y +CONFIG_EXTCON=y +CONFIG_EXTCON_USB_GPIO=y CONFIG_PWM=y -CONFIG_PHY_STARFIVE_JH7110_DPHY_RX=y -CONFIG_PHY_STARFIVE_JH7110_PCIE=y -CONFIG_PHY_STARFIVE_JH7110_USB=y +CONFIG_RESET_CONTROLLER=y +CONFIG_RESET_GPIO=y +CONFIG_NVMEM_LAYOUT_ONIE_TLV=y CONFIG_EXT2_FS=y -CONFIG_EXT2_FS_POSIX_ACL=y -CONFIG_EXT3_FS=y +CONFIG_EXT4_FS=y CONFIG_EXT4_FS_POSIX_ACL=y CONFIG_BTRFS_FS=y CONFIG_BTRFS_FS_POSIX_ACL=y CONFIG_FANOTIFY=y CONFIG_FANOTIFY_ACCESS_PERMISSIONS=y CONFIG_QUOTA=y -CONFIG_AUTOFS_FS=y CONFIG_FUSE_FS=y CONFIG_VIRTIO_FS=y CONFIG_OVERLAY_FS=y -CONFIG_MSDOS_FS=y CONFIG_VFAT_FS=y -CONFIG_FAT_DEFAULT_UTF8=y CONFIG_EXFAT_FS=y -CONFIG_NTFS_FS=y -CONFIG_NTFS_RW=y -CONFIG_PROC_KCORE=y -CONFIG_PROC_CHILDREN=y CONFIG_TMPFS=y CONFIG_TMPFS_POSIX_ACL=y -CONFIG_EFIVAR_FS=y -CONFIG_JFFS2_FS=y CONFIG_SQUASHFS=y CONFIG_SQUASHFS_LZO=y CONFIG_SQUASHFS_XZ=y CONFIG_SQUASHFS_ZSTD=y -CONFIG_NFS_FS=y -CONFIG_NFS_V4=y -CONFIG_NFS_V4_1=y -CONFIG_NFS_V4_2=y -CONFIG_ROOT_NFS=y CONFIG_9P_FS=y CONFIG_NLS_DEFAULT="iso8859-15" CONFIG_NLS_CODEPAGE_437=y @@ -457,40 +504,27 @@ CONFIG_NLS_ISO8859_1=y CONFIG_NLS_ISO8859_15=y CONFIG_NLS_UTF8=y CONFIG_SECURITY=y -CONFIG_LSM="" +CONFIG_LSM="landlock,lockdown,yama,loadpin,safesetid,bpf" CONFIG_CRYPTO_CCM=m CONFIG_CRYPTO_ECHAINIV=y -CONFIG_CRYPTO_ZSTD=y CONFIG_CRYPTO_ANSI_CPRNG=y -# CONFIG_RAID6_PQ_BENCHMARK is not set CONFIG_DMA_CMA=y CONFIG_CMA_SIZE_MBYTES=0 CONFIG_IRQ_POLL=y CONFIG_PRINTK_TIME=y -# CONFIG_DEBUG_MISC is not set +CONFIG_DEBUG_KERNEL=y CONFIG_DEBUG_INFO_DWARF_TOOLCHAIN_DEFAULT=y -CONFIG_STRIP_ASM_SYMS=y -CONFIG_DEBUG_SECTION_MISMATCH=y -# CONFIG_SECTION_MISMATCH_WARN_ONLY is not set CONFIG_MAGIC_SYSRQ=y CONFIG_DEBUG_FS=y -# CONFIG_SLUB_DEBUG is not set -CONFIG_DEBUG_RODATA_TEST=y -CONFIG_DEBUG_WX=y CONFIG_PANIC_ON_OOPS=y CONFIG_PANIC_TIMEOUT=20 CONFIG_BOOTPARAM_SOFTLOCKUP_PANIC=y CONFIG_HARDLOCKUP_DETECTOR=y -CONFIG_HARDLOCKUP_DETECTOR_PREFER_BUDDY=y CONFIG_BOOTPARAM_HARDLOCKUP_PANIC=y CONFIG_BOOTPARAM_HUNG_TASK_PANIC=y CONFIG_WQ_WATCHDOG=y CONFIG_WQ_CPU_INTENSIVE_REPORT=y CONFIG_TEST_LOCKUP=m -# CONFIG_SCHED_DEBUG is not set -CONFIG_STACKTRACE=y -CONFIG_RCU_CPU_STALL_TIMEOUT=60 # CONFIG_RCU_TRACE is not set -# CONFIG_FTRACE is not set -# CONFIG_RUNTIME_TESTING_MENU is not set +CONFIG_FUNCTION_TRACER=y CONFIG_MEMTEST=y diff --git a/board/riscv64/starfive-visionfive2/Config.in b/board/riscv64/starfive-visionfive2/Config.in new file mode 100644 index 0000000000..26c9c5333a --- /dev/null +++ b/board/riscv64/starfive-visionfive2/Config.in @@ -0,0 +1,6 @@ +config BR2_PACKAGE_STARFIVE_VISIONFIVE2 + bool "StarFive VisionFive2" + depends on BR2_RISCV_64 + select SDCARD_AUX + help + Support for the StarFive VisionFive2, based on the JH7110 SoC. diff --git a/board/riscv64/starfive-visionfive2/LICENSE b/board/riscv64/starfive-visionfive2/LICENSE new file mode 100644 index 0000000000..8cdb30a3aa --- /dev/null +++ b/board/riscv64/starfive-visionfive2/LICENSE @@ -0,0 +1,13 @@ +Copyright (c) 2026 The KernelKit Authors + +Permission to use, copy, modify, and/or distribute this software for any +purpose with or without fee is hereby granted, provided that the above +copyright notice and this permission notice appear in all copies. + +THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES +WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF +MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR +ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES +WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN +ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF +OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. diff --git a/board/riscv64/starfive-visionfive2/README.md b/board/riscv64/starfive-visionfive2/README.md index 64c95fb6d7..10c90793c8 100644 --- a/board/riscv64/starfive-visionfive2/README.md +++ b/board/riscv64/starfive-visionfive2/README.md @@ -11,15 +11,17 @@ How to Build ------------ ``` -$ make visionfive2_defconfig +$ make O=x-boot visionfive2_boot_defconfig +$ make O=x-boot +$ make riscv64_defconfig $ make +$ ./utils/mkimage.sh -b x-boot -r output starfive-visionfive2 ``` -Once the build has finished you will have `output/images/sdcard.img` -which you can flash to an SD card. +The image is `x-boot/images/infix-visionfive2-sdcard.img`: ``` -$ sudo dd if=output/images/sdcard.img of=/dev/mmcblk0 bs=1M status=progress oflag=direct +$ sudo dd if=x-boot/images/infix-visionfive2-sdcard.img of=/dev/mmcblk0 bs=1M status=progress oflag=direct ``` > **WARNING:** ensure `/dev/mmcblk0` really is the correct device for diff --git a/board/riscv64/starfive-visionfive2/board.mk b/board/riscv64/starfive-visionfive2/board.mk deleted file mode 100644 index e69de29bb2..0000000000 diff --git a/board/riscv64/starfive-visionfive2/dts/Makefile b/board/riscv64/starfive-visionfive2/dts/Makefile new file mode 100644 index 0000000000..8cfce30f5d --- /dev/null +++ b/board/riscv64/starfive-visionfive2/dts/Makefile @@ -0,0 +1 @@ +dtb-y += starfive/jh7110-starfive-visionfive-2-v1.2a.dtb starfive/jh7110-starfive-visionfive-2-v1.3b.dtb diff --git a/board/riscv64/starfive-visionfive2/dts/starfive/infix.dtsi b/board/riscv64/starfive-visionfive2/dts/starfive/infix.dtsi new file mode 100644 index 0000000000..16cfafc86d --- /dev/null +++ b/board/riscv64/starfive-visionfive2/dts/starfive/infix.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Common Infix OS defaults + */ + +/ { + chosen { + infix { + /* Default admin user password: 'admin' */ + factory-password-hash = "$5$mI/zpOAqZYKLC2WU$i7iPzZiIjOjrBF3NyftS9CCq8dfYwHwrmUK097Jca9A"; + }; + }; +}; diff --git a/board/riscv64/starfive-visionfive2/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts b/board/riscv64/starfive-visionfive2/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts new file mode 100644 index 0000000000..91e7ddbbbc --- /dev/null +++ b/board/riscv64/starfive-visionfive2/dts/starfive/jh7110-starfive-visionfive-2-v1.2a.dts @@ -0,0 +1,2 @@ +#include +#include "infix.dtsi" diff --git a/board/riscv64/starfive-visionfive2/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts b/board/riscv64/starfive-visionfive2/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts new file mode 100644 index 0000000000..d43f744f2d --- /dev/null +++ b/board/riscv64/starfive-visionfive2/dts/starfive/jh7110-starfive-visionfive-2-v1.3b.dts @@ -0,0 +1,2 @@ +#include +#include "infix.dtsi" diff --git a/board/riscv64/starfive-visionfive2/genimage.cfg b/board/riscv64/starfive-visionfive2/genimage.cfg.in similarity index 71% rename from board/riscv64/starfive-visionfive2/genimage.cfg rename to board/riscv64/starfive-visionfive2/genimage.cfg.in index 0d48b36caf..2e06b08d6b 100644 --- a/board/riscv64/starfive-visionfive2/genimage.cfg +++ b/board/riscv64/starfive-visionfive2/genimage.cfg.in @@ -1,5 +1,3 @@ -# Infix SD card image for the Starfive VisionFive2 - image cfg.ext4 { empty = true temporary = true @@ -8,21 +6,27 @@ image cfg.ext4 { ext4 { label = "cfg" use-mke2fs = true + features = "uninit_bg" + extraargs = "-m 0 -i 4096" } } +# The /var partition will be expanded automatically at first boot +# to use the full size of the SD-card or eMMC media. image var.ext4 { empty = true temporary = true - size = 512M + size = 128M ext4 { label = "var" use-mke2fs = true + features = "uninit_bg" + extraargs = "-m 0 -i 4096" } } -image sdcard.img { +image #IX_ID##VERSION#-visionfive2-sdcard.img { hdimage { partition-table-type = "gpt" } @@ -39,21 +43,20 @@ image sdcard.img { partition aux { partition-uuid = D4EF35A0-0652-45A1-B3DE-D63339C82035 - # Created by mkaux.sh image = "aux.ext4" } partition primary { - partition-type-uuid = 0FC63DAF-8483-4772-8E79-3D69D8477DE4 + partition-type-uuid = linux bootable = true - size = 200M + size = 250M image = "rootfs.squashfs" } partition secondary { - partition-type-uuid = 0FC63DAF-8483-4772-8E79-3D69D8477DE4 + partition-type-uuid = linux bootable = true - size = 200M + size = 250M image = "rootfs.squashfs" } @@ -67,6 +70,3 @@ image sdcard.img { image = "var.ext4" } } - -# Silence genimage warnings -config {} diff --git a/board/riscv64/starfive-visionfive2/jh7110-starfive-visionfive-2-dtsi.patch b/board/riscv64/starfive-visionfive2/jh7110-starfive-visionfive-2-dtsi.patch deleted file mode 100644 index 38c6f023a9..0000000000 --- a/board/riscv64/starfive-visionfive2/jh7110-starfive-visionfive-2-dtsi.patch +++ /dev/null @@ -1,14 +0,0 @@ ---- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -+++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi -@@ -24,6 +24,11 @@ aliases { - - chosen { - stdout-path = "serial0:115200n8"; -+ -+ infix { -+ /* Default admin user password: 'admin' */ -+ factory-password-hash = "$5$mI/zpOAqZYKLC2WU$i7iPzZiIjOjrBF3NyftS9CCq8dfYwHwrmUK097Jca9A"; -+ }; - }; - - cpus { diff --git a/board/riscv64/starfive-visionfive2/starfive-visionfive2.hash b/board/riscv64/starfive-visionfive2/starfive-visionfive2.hash new file mode 100644 index 0000000000..2b1e744325 --- /dev/null +++ b/board/riscv64/starfive-visionfive2/starfive-visionfive2.hash @@ -0,0 +1,2 @@ +# Locally calculated +sha256 d48246c717b505cc11df95171f2fd548b389e1a463f1af4c68d0b69fe0d1009b LICENSE diff --git a/board/riscv64/starfive-visionfive2/starfive-visionfive2.mk b/board/riscv64/starfive-visionfive2/starfive-visionfive2.mk new file mode 100644 index 0000000000..463b1a7906 --- /dev/null +++ b/board/riscv64/starfive-visionfive2/starfive-visionfive2.mk @@ -0,0 +1,52 @@ +define STARFIVE_VISIONFIVE2_LINUX_CONFIG_FIXUPS + $(call KCONFIG_ENABLE_OPT,CONFIG_SOC_STARFIVE) + $(call KCONFIG_ENABLE_OPT,CONFIG_ERRATA_SIFIVE) + $(call KCONFIG_ENABLE_OPT,CONFIG_SIFIVE_CCACHE) + $(call KCONFIG_ENABLE_OPT,CONFIG_CLK_STARFIVE_JH7110_SYS) + $(call KCONFIG_ENABLE_OPT,CONFIG_CLK_STARFIVE_JH7110_AON) + $(call KCONFIG_ENABLE_OPT,CONFIG_CLK_STARFIVE_JH7110_STG) + $(call KCONFIG_ENABLE_OPT,CONFIG_PINCTRL_STARFIVE_JH7110_SYS) + $(call KCONFIG_ENABLE_OPT,CONFIG_PINCTRL_STARFIVE_JH7110_AON) + $(call KCONFIG_ENABLE_OPT,CONFIG_RESET_STARFIVE_JH7110) + $(call KCONFIG_ENABLE_OPT,CONFIG_JH71XX_PMU) + $(call KCONFIG_ENABLE_OPT,CONFIG_SERIAL_8250) + $(call KCONFIG_ENABLE_OPT,CONFIG_SERIAL_8250_CONSOLE) + $(call KCONFIG_ENABLE_OPT,CONFIG_SERIAL_8250_DW) + $(call KCONFIG_ENABLE_OPT,CONFIG_SERIAL_OF_PLATFORM) + $(call KCONFIG_ENABLE_OPT,CONFIG_NET_VENDOR_STMICRO) + $(call KCONFIG_ENABLE_OPT,CONFIG_STMMAC_ETH) + $(call KCONFIG_ENABLE_OPT,CONFIG_DWMAC_STARFIVE) + $(call KCONFIG_ENABLE_OPT,CONFIG_MOTORCOMM_PHY) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMC) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMC_DW) + $(call KCONFIG_ENABLE_OPT,CONFIG_MMC_DW_STARFIVE) + $(call KCONFIG_ENABLE_OPT,CONFIG_PCIE_STARFIVE_HOST) + $(call KCONFIG_ENABLE_OPT,CONFIG_PHY_STARFIVE_JH7110_PCIE) + $(call KCONFIG_ENABLE_OPT,CONFIG_PHY_STARFIVE_JH7110_USB) + $(call KCONFIG_SET_OPT,CONFIG_USB_XHCI_PCI,m) + $(call KCONFIG_ENABLE_OPT,CONFIG_USB_CDNS_SUPPORT) + $(call KCONFIG_ENABLE_OPT,CONFIG_USB_CDNS3) + $(call KCONFIG_ENABLE_OPT,CONFIG_USB_CDNS3_HOST) + $(call KCONFIG_ENABLE_OPT,CONFIG_USB_CDNS3_STARFIVE) + $(call KCONFIG_ENABLE_OPT,CONFIG_I2C_DESIGNWARE_CORE) + $(call KCONFIG_ENABLE_OPT,CONFIG_I2C_DESIGNWARE_PLATFORM) + $(call KCONFIG_ENABLE_OPT,CONFIG_MFD_AXP20X_I2C) + $(call KCONFIG_ENABLE_OPT,CONFIG_REGULATOR_AXP20X) + $(call KCONFIG_ENABLE_OPT,CONFIG_EEPROM_AT24) + $(call KCONFIG_ENABLE_OPT,CONFIG_SPI_CADENCE_QUADSPI) + $(call KCONFIG_ENABLE_OPT,CONFIG_SPI_PL022) + $(call KCONFIG_ENABLE_OPT,CONFIG_MTD_SPI_NOR) + $(call KCONFIG_ENABLE_OPT,CONFIG_DW_AXI_DMAC) + $(call KCONFIG_ENABLE_OPT,CONFIG_AMBA_PL08X) + $(call KCONFIG_ENABLE_OPT,CONFIG_HW_RANDOM) + $(call KCONFIG_ENABLE_OPT,CONFIG_HW_RANDOM_JH7110) + $(call KCONFIG_SET_OPT,CONFIG_CRYPTO_DEV_JH7110,m) + $(call KCONFIG_ENABLE_OPT,CONFIG_STARFIVE_WATCHDOG) + $(call KCONFIG_SET_OPT,CONFIG_SENSORS_SFCTEMP,m) + $(call KCONFIG_ENABLE_OPT,CONFIG_CPUFREQ_DT) + $(call KCONFIG_ENABLE_OPT,CONFIG_POWER_RESET_GPIO_RESTART) + $(call KCONFIG_ENABLE_OPT,CONFIG_LEDS_GPIO) +endef + +$(eval $(ix-board)) +$(eval $(generic-package)) diff --git a/configs/bpi_f3_boot_defconfig b/configs/bpi_f3_boot_defconfig new file mode 100644 index 0000000000..33e9925fd6 --- /dev/null +++ b/configs/bpi_f3_boot_defconfig @@ -0,0 +1,42 @@ +BR2_riscv=y +BR2_TOOLCHAIN_EXTERNAL=y +BR2_DL_DIR="$(BR2_EXTERNAL_INFIX_PATH)/dl" +BR2_CCACHE=y +BR2_CCACHE_DIR="$(BR2_EXTERNAL_INFIX_PATH)/.ccache" +BR2_ENABLE_DEBUG=y +BR2_PACKAGE_OVERRIDE_FILE="$(BR2_EXTERNAL_INFIX_PATH)/local.mk" +BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_INFIX_PATH)/patches" +BR2_SSP_NONE=y +BR2_INIT_NONE=y +BR2_SYSTEM_BIN_SH_NONE=y +# BR2_TARGET_ROOTFS_TAR is not set +BR2_TARGET_OPENSBI=y +BR2_TARGET_OPENSBI_CUSTOM_VERSION=y +BR2_TARGET_OPENSBI_CUSTOM_VERSION_VALUE="1.8.1" +BR2_TARGET_OPENSBI_PLAT="generic" +# BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG is not set +BR2_TARGET_UBOOT=y +BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y +BR2_TARGET_UBOOT_CUSTOM_GIT=y +BR2_TARGET_UBOOT_CUSTOM_REPO_URL="https://github.com/kernelkit/u-boot.git" +BR2_TARGET_UBOOT_CUSTOM_REPO_VERSION="bee4e853602705860b5be3ab74fc7d65ddac69d6" +BR2_TARGET_UBOOT_BOARD_DEFCONFIG="spacemit_k1" +BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_INFIX_PATH)/board/common/uboot/extras.config $(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/bananapi-bpi-f3/uboot/extras.config" +BR2_TARGET_UBOOT_NEEDS_DTC=y +BR2_TARGET_UBOOT_NEEDS_PYLIBFDT=y +BR2_TARGET_UBOOT_NEEDS_OPENSSL=y +BR2_TARGET_UBOOT_NEEDS_OPENSBI=y +# BR2_TARGET_UBOOT_FORMAT_BIN is not set +BR2_TARGET_UBOOT_FORMAT_CUSTOM=y +BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot.itb" +BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/bananapi-bpi-f3/uboot/bpi-f3-env.dtsi" +BR2_PACKAGE_HOST_BMAP_TOOLS=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_RAUC=y +BR2_PACKAGE_HOST_UBOOT_TOOLS=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SUPPORT=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SIGNATURE_SUPPORT=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_FDT_ADD_PUBKEY=y +BR2_PACKAGE_SPACEMIT_K1_FSBL=y +IX_TRUSTED_KEYS=y +IX_TRUSTED_KEYS_DEVELOPMENT=y diff --git a/configs/riscv64_defconfig b/configs/riscv64_defconfig index 4b83addffb..d976c6c082 100644 --- a/configs/riscv64_defconfig +++ b/configs/riscv64_defconfig @@ -1,5 +1,6 @@ BR2_riscv=y BR2_TOOLCHAIN_EXTERNAL=y +BR2_TOOLCHAIN_EXTERNAL_BOOTLIN=y BR2_TOOLCHAIN_EXTERNAL_GDB_SERVER_COPY=y BR2_DL_DIR="${BR2_EXTERNAL_INFIX_PATH}/dl" BR2_CCACHE=y @@ -21,32 +22,19 @@ BR2_ENABLE_LOCALE_WHITELIST="C en_US en_CA C.UTF-8" BR2_GENERATE_LOCALE="en_US en_CA C.UTF-8" BR2_TARGET_TZ_INFO=y BR2_ROOTFS_OVERLAY="${BR2_EXTERNAL_INFIX_PATH}/board/common/rootfs ${BR2_EXTERNAL_INFIX_PATH}/board/riscv64/rootfs" -BR2_ROOTFS_POST_BUILD_SCRIPT="$(BR2_EXTERNAL_INFIX_PATH)/board/common/post-build.sh" -BR2_ROOTFS_POST_IMAGE_SCRIPT="support/scripts/genimage.sh" -BR2_ROOTFS_POST_SCRIPT_ARGS="-c $(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/visionfive2/genimage.cfg" +BR2_ROOTFS_POST_BUILD_SCRIPT="${BR2_EXTERNAL_INFIX_PATH}/board/common/post-build.sh" BR2_LINUX_KERNEL=y BR2_LINUX_KERNEL_CUSTOM_VERSION=y -BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.8.2" -BR2_LINUX_KERNEL_PATCH="$(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/visionfive2/jh7110-starfive-visionfive-2-dtsi.patch" +BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="6.18.56" BR2_LINUX_KERNEL_USE_CUSTOM_CONFIG=y BR2_LINUX_KERNEL_CUSTOM_CONFIG_FILE="${BR2_EXTERNAL_INFIX_PATH}/board/riscv64/linux_defconfig" -BR2_LINUX_KERNEL_DTS_SUPPORT=y -BR2_LINUX_KERNEL_INTREE_DTS_NAME="starfive/jh7110-starfive-visionfive-2-v1.3b" -BR2_LINUX_KERNEL_DTB_KEEP_DIRNAME=y BR2_LINUX_KERNEL_INSTALL_TARGET=y -BR2_LINUX_KERNEL_NEEDS_HOST_OPENSSL=y BR2_PACKAGE_BUSYBOX_CONFIG="${BR2_EXTERNAL_INFIX_PATH}/board/common/busybox_defconfig" BR2_PACKAGE_STRACE=y BR2_PACKAGE_STRESS_NG=y BR2_PACKAGE_JQ=y BR2_PACKAGE_E2FSPROGS=y BR2_PACKAGE_E2FSPROGS_RESIZE2FS=y -BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT61=y -BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT73=y -BR2_PACKAGE_LINUX_FIRMWARE_RALINK_RT2XX=y -BR2_PACKAGE_LINUX_FIRMWARE_RTL_87XX=y -BR2_PACKAGE_LINUX_FIRMWARE_RTL_88XX=y -BR2_PACKAGE_LINUX_FIRMWARE_RTL_815X=y BR2_PACKAGE_DBUS_CXX=y BR2_PACKAGE_DBUS_GLIB=y BR2_PACKAGE_EUDEV_RULES_GEN=y @@ -55,6 +43,7 @@ BR2_PACKAGE_GPTFDISK=y BR2_PACKAGE_GPTFDISK_SGDISK=y BR2_PACKAGE_MDIO_TOOLS=y BR2_PACKAGE_RNG_TOOLS=y +BR2_PACKAGE_UBOOT_TOOLS=y BR2_PACKAGE_UBOOT_TOOLS_FIT_SUPPORT=y BR2_PACKAGE_UBOOT_TOOLS_FIT_SIGNATURE_SUPPORT=y BR2_PACKAGE_UBOOT_TOOLS_FIT_CHECK_SIGN=y @@ -136,40 +125,17 @@ BR2_PACKAGE_WATCHDOGD_TEMPMON=y BR2_PACKAGE_LESS=y BR2_PACKAGE_MG=y BR2_PACKAGE_NANO=y -BR2_TARGET_ROOTFS_EXT2=y -BR2_TARGET_ROOTFS_EXT2_4=y -BR2_TARGET_ROOTFS_EXT2_SIZE="512M" -BR2_TARGET_ROOTFS_EXT2_INODE_SIZE=0 -BR2_TARGET_ROOTFS_EXT2_MKFS_OPTIONS="-O ^64bit,large_file,ext_attr" # BR2_TARGET_ROOTFS_TAR is not set -BR2_TARGET_OPENSBI=y -BR2_TARGET_OPENSBI_CUSTOM_VERSION=y -BR2_TARGET_OPENSBI_CUSTOM_VERSION_VALUE="1.4" -BR2_TARGET_OPENSBI_PLAT="generic" -# BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG is not set -BR2_TARGET_OPENSBI_ADDITIONAL_VARIABLES="FW_TEXT_START=0x40000000 FW_OPTIONS=0" -BR2_TARGET_UBOOT=y -BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y -BR2_TARGET_UBOOT_CUSTOM_VERSION=y -BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2024.07" -BR2_TARGET_UBOOT_BOARD_DEFCONFIG="starfive_visionfive2" -BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_INFIX_PATH)/board/common/uboot/extras.config $(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/visionfive2/uboot/extras.config" -BR2_TARGET_UBOOT_NEEDS_DTC=y -BR2_TARGET_UBOOT_NEEDS_PYLIBFDT=y -BR2_TARGET_UBOOT_NEEDS_OPENSSL=y -BR2_TARGET_UBOOT_NEEDS_OPENSBI=y -# BR2_TARGET_UBOOT_FORMAT_BIN is not set -BR2_TARGET_UBOOT_FORMAT_DTB=y -BR2_TARGET_UBOOT_FORMAT_CUSTOM=y -BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot.itb" -BR2_TARGET_UBOOT_SPL=y -BR2_TARGET_UBOOT_SPL_NAME="spl/u-boot-spl.bin.normal.out" -BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/visionfive2/uboot/visionfive2-env.dtsi" BR2_PACKAGE_HOST_BMAP_TOOLS=y +BR2_PACKAGE_HOST_E2FSPROGS=y +BR2_PACKAGE_HOST_ENVIRONMENT_SETUP=y +BR2_PACKAGE_HOST_GENEXT2FS=y BR2_PACKAGE_HOST_GO_BIN=y BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SUPPORT=y BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SIGNATURE_SUPPORT=y BR2_PACKAGE_HOST_UBOOT_TOOLS_FDT_ADD_PUBKEY=y +BR2_PACKAGE_BANANAPI_BPI_F3=y +BR2_PACKAGE_STARFIVE_VISIONFIVE2=y IX_VENDOR_HOME="https://www.kernelkit.org" IX_DESC="Infix is an immutable, friendly, and secure operating system that turns any ARM or x86 device into a powerful, manageable network appliance. Deploy on anything from $35 Raspberry Pi boards to enterprise switches as routers, IoT gateways, or edge devices. Infix models Linux networking features using YANG so you can manage your devices using NETCONF/RESTCONF APIs and focus on your business logic running in isolated containers." IX_HOME="https://github.com/kernelkit/infix/" @@ -182,6 +148,7 @@ BR2_PACKAGE_FEATURE_WIFI_QUALCOMM=y BR2_PACKAGE_FEATURE_WIFI_REALTEK=y BR2_PACKAGE_CONFD=y BR2_PACKAGE_NETD=y +BR2_PACKAGE_CONFD_TEST_MODE=y BR2_PACKAGE_GENCERT=y BR2_PACKAGE_STATD=y BR2_PACKAGE_SUPPORT_ENCRYPT=y diff --git a/configs/visionfive2_boot_defconfig b/configs/visionfive2_boot_defconfig new file mode 100644 index 0000000000..a27600a13b --- /dev/null +++ b/configs/visionfive2_boot_defconfig @@ -0,0 +1,44 @@ +BR2_riscv=y +BR2_TOOLCHAIN_EXTERNAL=y +BR2_DL_DIR="$(BR2_EXTERNAL_INFIX_PATH)/dl" +BR2_CCACHE=y +BR2_CCACHE_DIR="$(BR2_EXTERNAL_INFIX_PATH)/.ccache" +BR2_ENABLE_DEBUG=y +BR2_PACKAGE_OVERRIDE_FILE="$(BR2_EXTERNAL_INFIX_PATH)/local.mk" +BR2_GLOBAL_PATCH_DIR="$(BR2_EXTERNAL_INFIX_PATH)/patches" +BR2_SSP_NONE=y +BR2_INIT_NONE=y +BR2_SYSTEM_BIN_SH_NONE=y +# BR2_TARGET_ROOTFS_TAR is not set +BR2_TARGET_OPENSBI=y +BR2_TARGET_OPENSBI_CUSTOM_VERSION=y +BR2_TARGET_OPENSBI_CUSTOM_VERSION_VALUE="1.4" +BR2_TARGET_OPENSBI_PLAT="generic" +# BR2_TARGET_OPENSBI_INSTALL_JUMP_IMG is not set +BR2_TARGET_OPENSBI_ADDITIONAL_VARIABLES="FW_TEXT_START=0x40000000 FW_OPTIONS=0" +BR2_TARGET_UBOOT=y +BR2_TARGET_UBOOT_BUILD_SYSTEM_KCONFIG=y +BR2_TARGET_UBOOT_CUSTOM_VERSION=y +BR2_TARGET_UBOOT_CUSTOM_VERSION_VALUE="2024.07" +BR2_TARGET_UBOOT_BOARD_DEFCONFIG="starfive_visionfive2" +BR2_TARGET_UBOOT_CONFIG_FRAGMENT_FILES="$(BR2_EXTERNAL_INFIX_PATH)/board/common/uboot/extras.config $(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/starfive-visionfive2/uboot/extras.config" +BR2_TARGET_UBOOT_NEEDS_DTC=y +BR2_TARGET_UBOOT_NEEDS_PYLIBFDT=y +BR2_TARGET_UBOOT_NEEDS_OPENSSL=y +BR2_TARGET_UBOOT_NEEDS_OPENSBI=y +# BR2_TARGET_UBOOT_FORMAT_BIN is not set +BR2_TARGET_UBOOT_FORMAT_DTB=y +BR2_TARGET_UBOOT_FORMAT_CUSTOM=y +BR2_TARGET_UBOOT_FORMAT_CUSTOM_NAME="u-boot.itb" +BR2_TARGET_UBOOT_SPL=y +BR2_TARGET_UBOOT_SPL_NAME="spl/u-boot-spl.bin.normal.out" +BR2_TARGET_UBOOT_CUSTOM_DTS_PATH="$(BR2_EXTERNAL_INFIX_PATH)/board/riscv64/starfive-visionfive2/uboot/visionfive2-env.dtsi" +BR2_PACKAGE_HOST_BMAP_TOOLS=y +BR2_PACKAGE_HOST_GENIMAGE=y +BR2_PACKAGE_HOST_RAUC=y +BR2_PACKAGE_HOST_UBOOT_TOOLS=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SUPPORT=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_FIT_SIGNATURE_SUPPORT=y +BR2_PACKAGE_HOST_UBOOT_TOOLS_FDT_ADD_PUBKEY=y +IX_TRUSTED_KEYS=y +IX_TRUSTED_KEYS_DEVELOPMENT=y diff --git a/package/Config.in b/package/Config.in index f91fb55803..88810954c1 100644 --- a/package/Config.in +++ b/package/Config.in @@ -40,6 +40,7 @@ source "$BR2_EXTERNAL_INFIX_PATH/package/python-spy/Config.in" source "$BR2_EXTERNAL_INFIX_PATH/package/python-libyang/Config.in" source "$BR2_EXTERNAL_INFIX_PATH/package/python-yangdoc/Config.in" source "$BR2_EXTERNAL_INFIX_PATH/package/skeleton-init-finit/Config.in" +source "$BR2_EXTERNAL_INFIX_PATH/package/spacemit-k1-fsbl/Config.in" source "$BR2_EXTERNAL_INFIX_PATH/package/tetris/Config.in" source "$BR2_EXTERNAL_INFIX_PATH/package/libyang-cpp/Config.in" source "$BR2_EXTERNAL_INFIX_PATH/package/sysrepo-cpp/Config.in" diff --git a/package/spacemit-k1-fsbl/Config.in b/package/spacemit-k1-fsbl/Config.in new file mode 100644 index 0000000000..c0b79c1e4c --- /dev/null +++ b/package/spacemit-k1-fsbl/Config.in @@ -0,0 +1,13 @@ +config BR2_PACKAGE_SPACEMIT_K1_FSBL + bool "spacemit-k1-fsbl" + depends on BR2_RISCV_64 + depends on BR2_TARGET_OPENSBI + help + First stage bootloader for the SpacemiT K1, the vendor U-Boot + SPL with DDR init, signed for the BootROM. Also wraps the + OpenSBI fw_dynamic.bin in the FIT image the FSBL loads from + the opensbi partition. + + Installs FSBL.bin, bootinfo_sd.bin and fw_dynamic.itb. + + https://gitee.com/spacemit-buildroot/uboot-2022.10 diff --git a/package/spacemit-k1-fsbl/fw_dynamic.its b/package/spacemit-k1-fsbl/fw_dynamic.its new file mode 100644 index 0000000000..f1159d4cfe --- /dev/null +++ b/package/spacemit-k1-fsbl/fw_dynamic.its @@ -0,0 +1,31 @@ +/dts-v1/; + +/ { + description = "Configuration to load OpenSBI before U-Boot"; + #address-cells = <2>; + fit,fdt-list = "of-list"; + + images { + opensbi { + description = "OpenSBI fw_dynamic Firmware"; + type = "firmware"; + os = "opensbi"; + arch = "riscv"; + compression = "none"; + load = <0x0 0x0>; + entry = <0x0 0x0>; + data = /incbin/("./fw_dynamic.bin"); + hash-1 { + algo = "crc32"; + }; + }; + }; + configurations { + default = "config_1"; + + config_1 { + description = "opensbi FIT config"; + firmware = "opensbi"; + }; + }; +}; diff --git a/package/spacemit-k1-fsbl/spacemit-k1-fsbl.hash b/package/spacemit-k1-fsbl/spacemit-k1-fsbl.hash new file mode 100644 index 0000000000..eff2a64d45 --- /dev/null +++ b/package/spacemit-k1-fsbl/spacemit-k1-fsbl.hash @@ -0,0 +1,3 @@ +# Locally calculated +sha256 a4360d623cde5d366c52c7c2ce9c50e9a07ec2246f79ef3e3098c3ff945e78cf spacemit-k1-fsbl-78fda8a0127e17b81e98464dd005c4fc1f8cada0-git4.tar.gz +sha256 8177f97513213526df2cf6184d8ff986c675afb514d4e68a404010521b880643 Licenses/gpl-2.0.txt diff --git a/package/spacemit-k1-fsbl/spacemit-k1-fsbl.mk b/package/spacemit-k1-fsbl/spacemit-k1-fsbl.mk new file mode 100644 index 0000000000..ef2785be36 --- /dev/null +++ b/package/spacemit-k1-fsbl/spacemit-k1-fsbl.mk @@ -0,0 +1,40 @@ +################################################################################ +# +# spacemit-k1-fsbl +# +################################################################################ + +SPACEMIT_K1_FSBL_VERSION = 78fda8a0127e17b81e98464dd005c4fc1f8cada0 +SPACEMIT_K1_FSBL_SITE = https://gitee.com/spacemit-buildroot/uboot-2022.10.git +SPACEMIT_K1_FSBL_SITE_METHOD = git +SPACEMIT_K1_FSBL_LICENSE = GPL-2.0+ +SPACEMIT_K1_FSBL_LICENSE_FILES = Licenses/gpl-2.0.txt +SPACEMIT_K1_FSBL_INSTALL_TARGET = NO +SPACEMIT_K1_FSBL_INSTALL_IMAGES = YES +SPACEMIT_K1_FSBL_DEPENDENCIES = $(BR2_BISON_HOST_DEPENDENCY) \ + $(BR2_FLEX_HOST_DEPENDENCY) host-dtc host-openssl host-python3 opensbi + +SPACEMIT_K1_FSBL_MAKE_OPTS = \ + CROSS_COMPILE="$(TARGET_CROSS)" \ + ARCH=riscv \ + HOSTCC="$(HOSTCC) $(subst -I/,-isystem /,$(subst -I /,-isystem /,$(HOST_CFLAGS)))" \ + HOSTLDFLAGS="$(HOST_LDFLAGS)" \ + DTC=$(HOST_DIR)/bin/dtc + +# Building the SPL also signs it into FSBL.bin. The OpenSBI FIT is +# made with the vendor mkimage: the FSBL checks a crc32 hash, and the +# mkimage from host-uboot-tools 2024.04 is built without crc32. +define SPACEMIT_K1_FSBL_BUILD_CMDS + $(TARGET_MAKE_ENV) $(MAKE) -C $(@D) $(SPACEMIT_K1_FSBL_MAKE_OPTS) k1_defconfig + $(TARGET_MAKE_ENV) $(MAKE) -C $(@D) $(SPACEMIT_K1_FSBL_MAKE_OPTS) spl/u-boot-spl + cp $(SPACEMIT_K1_FSBL_PKGDIR)/fw_dynamic.its $(BINARIES_DIR)/fw_dynamic.bin $(@D)/ + $(TARGET_MAKE_ENV) $(@D)/tools/mkimage -f $(@D)/fw_dynamic.its $(@D)/fw_dynamic.itb +endef + +define SPACEMIT_K1_FSBL_INSTALL_IMAGES_CMDS + $(INSTALL) -D -m 0644 $(@D)/FSBL.bin $(BINARIES_DIR)/FSBL.bin + $(INSTALL) -D -m 0644 $(@D)/bootinfo_sd.bin $(BINARIES_DIR)/bootinfo_sd.bin + $(INSTALL) -D -m 0644 $(@D)/fw_dynamic.itb $(BINARIES_DIR)/fw_dynamic.itb +endef + +$(eval $(generic-package)) diff --git a/patches/libgcrypt/1.11.1/0001-Fix-missing-simd-common-riscv.h-in-libgcrypt-tarball.patch b/patches/libgcrypt/1.11.1/0001-Fix-missing-simd-common-riscv.h-in-libgcrypt-tarball.patch new file mode 100644 index 0000000000..42f5522698 --- /dev/null +++ b/patches/libgcrypt/1.11.1/0001-Fix-missing-simd-common-riscv.h-in-libgcrypt-tarball.patch @@ -0,0 +1,85 @@ +From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 +From: Collin Funk via Gcrypt-devel +Date: Fri, 16 May 2025 21:10:37 -0700 +Subject: [PATCH] Fix missing simd-common-riscv.h in libgcrypt tarball. + +* cipher/Makefile.am (EXTRA_libcipher_la_SOURCES): Add +simd-common-riscv.h. + +-- + +GnuPG-bug-id: 7647 +Signed-off-by: Collin Funk + +[ backport: the 1.11.1 tarball lacks the header itself, so add it here + as well, unchanged from the libgcrypt-1.11.1 tag ] + +Upstream: https://github.com/gpg/libgcrypt/commit/62f84bb3040fc138f061032889574f82ce72a0bc +--- +diff --git a/cipher/Makefile.am b/cipher/Makefile.am +index c33cce0a..2e129cab 100644 +--- a/cipher/Makefile.am ++++ b/cipher/Makefile.am +@@ -129,7 +129,7 @@ EXTRA_libcipher_la_SOURCES = \ + seed.c \ + serpent.c serpent-sse2-amd64.S serpent-avx2-amd64.S \ + serpent-avx512-x86.c serpent-armv7-neon.S \ +- simd-common-aarch64.h simd-common-ppc.h \ ++ simd-common-aarch64.h simd-common-ppc.h simd-common-riscv.h \ + sm4.c sm4-aesni-avx-amd64.S sm4-aesni-avx2-amd64.S \ + sm4-gfni-avx2-amd64.S sm4-gfni-avx512-amd64.S \ + sm4-aarch64.S sm4-armv8-aarch64-ce.S sm4-armv9-aarch64-sve-ce.S \ +diff --git a/cipher/simd-common-riscv.h b/cipher/simd-common-riscv.h +new file mode 100644 +index 00000000..8381000f +--- /dev/null ++++ b/cipher/simd-common-riscv.h +@@ -0,0 +1,48 @@ ++/* simd-common-riscv.h - Common macros for RISC-V vector code ++ * ++ * Copyright (C) 2025 Jussi Kivilinna ++ * ++ * This file is part of Libgcrypt. ++ * ++ * Libgcrypt is free software; you can redistribute it and/or modify ++ * it under the terms of the GNU Lesser General Public License as ++ * published by the Free Software Foundation; either version 2.1 of ++ * the License, or (at your option) any later version. ++ * ++ * Libgcrypt is distributed in the hope that it will be useful, ++ * but WITHOUT ANY WARRANTY; without even the implied warranty of ++ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ++ * GNU Lesser General Public License for more details. ++ * ++ * You should have received a copy of the GNU Lesser General Public ++ * License along with this program; if not, see . ++ */ ++ ++#ifndef GCRY_SIMD_COMMON_RISCV_H ++#define GCRY_SIMD_COMMON_RISCV_H ++ ++#include ++ ++#define memory_barrier_with_vec(a) __asm__("" : "+vr"(a) :: "memory") ++ ++#define clear_vec_regs() __asm__ volatile("vsetvli zero, %0, e8, m1, ta, ma;\n" \ ++ "vmv.v.i v0, 0;\n" \ ++ "vmv.v.i v1, 0;\n" \ ++ "vmv2r.v v2, v0;\n" \ ++ "vmv4r.v v4, v0;\n" \ ++ "vmv8r.v v8, v0;\n" \ ++ "vmv8r.v v16, v0;\n" \ ++ "vmv8r.v v24, v0;\n" \ ++ : \ ++ : "r" (~0) \ ++ : "memory", "vl", "vtype", \ ++ "v0", "v1", "v2", "v3", \ ++ "v4", "v5", "v6", "v7", \ ++ "v8", "v9", "v10", "v11", \ ++ "v12", "v13", "v14", "v15", \ ++ "v16", "v17", "v18", "v19", \ ++ "v20", "v21", "v22", "v23", \ ++ "v24", "v25", "v26", "v27", \ ++ "v28", "v29", "v30", "v31") ++ ++#endif /* GCRY_SIMD_COMMON_RISCV_H */ diff --git a/patches/linux/6.18.56/0087-riscv-dts-spacemit-add-UART-pinctrl-combinations.patch b/patches/linux/6.18.56/0087-riscv-dts-spacemit-add-UART-pinctrl-combinations.patch new file mode 100644 index 0000000000..2eb2d12a3d --- /dev/null +++ b/patches/linux/6.18.56/0087-riscv-dts-spacemit-add-UART-pinctrl-combinations.patch @@ -0,0 +1,465 @@ +From 48c77340af8c65ca397f9566482107efcaf6e438 Mon Sep 17 00:00:00 2001 +From: Hendrik Hamerlinck +Date: Wed, 17 Sep 2025 08:59:07 +0200 +Subject: [PATCH 087/100] riscv: dts: spacemit: add UART pinctrl combinations + +Add UART pinctrl configurations based on the SoC datasheet and the +downstream Bianbu Linux tree. The drive strength values were taken from +the downstream implementation, which uses medium drive strength. +CTS/RTS are moved to separate *-cts-rts-cfg states so boards can enable +hardware flow control conditionally. + +Signed-off-by: Hendrik Hamerlinck +Reviewed-by: Yixun Lan +Reviewed-by: Troy Mitchell +Link: https://lore.kernel.org/r/20250917065907.160615-1-hendrik.hamerlinck@hammernet.be +Signed-off-by: Yixun Lan +(cherry picked from commit 1187f9b3f6ebde806289877fa710ffd58f950104) +--- + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 430 ++++++++++++++++++- + 1 file changed, 428 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index 48c4b4131164..09a4f1dca4f1 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -75,11 +75,437 @@ gmac1-clk-ref-pins { + }; + }; + ++ /omit-if-no-ref/ ++ uart0_0_cfg: uart0-0-cfg { ++ uart0-0-pins { ++ pinmux = , /* uart0_txd */ ++ ; /* uart0_rxd */ ++ power-source = <3300>; ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart0_1_cfg: uart0-1-cfg { ++ uart0-1-pins { ++ pinmux = , /* uart0_txd */ ++ ; /* uart0_rxd */ ++ power-source = <3300>; ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ + uart0_2_cfg: uart0-2-cfg { + uart0-2-pins { +- pinmux = , +- ; ++ pinmux = , /* uart0_txd */ ++ ; /* uart0_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_0_cfg: uart2-0-cfg { ++ uart2-0-pins { ++ pinmux = , /* uart2_txd */ ++ ; /* uart2_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart2_0_cts_rts_cfg: uart2-0-cts-rts-cfg { ++ uart2-0-pins { ++ pinmux = , /* uart2_cts */ ++ ; /* uart2_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_0_cfg: uart3-0-cfg { ++ uart3-0-pins { ++ pinmux = , /* uart3_txd */ ++ ; /* uart3_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_0_cts_rts_cfg: uart3-0-cts-rts-cfg { ++ uart3-0-pins { ++ pinmux = , /* uart3_cts */ ++ ; /* uart3_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_1_cfg: uart3-1-cfg { ++ uart3-1-pins { ++ pinmux = , /* uart3_txd */ ++ ; /* uart3_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_1_cts_rts_cfg: uart3-1-cts-rts-cfg { ++ uart3-1-pins { ++ pinmux = , /* uart3_cts */ ++ ; /* uart3_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_2_cfg: uart3-2-cfg { ++ uart3-2-pins { ++ pinmux = , /* uart3_txd */ ++ ; /* uart3_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart3_2_cts_rts_cfg: uart3-2-cts-rts-cfg { ++ uart3-2-pins { ++ pinmux = , /* uart3_cts */ ++ ; /* uart3_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_0_cfg: uart4-0-cfg { ++ uart4-0-pins { ++ pinmux = , /* uart4_txd */ ++ ; /* uart4_rxd */ ++ power-source = <3300>; ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_1_cfg: uart4-1-cfg { ++ uart4-1-pins { ++ pinmux = , /* uart4_txd */ ++ ; /* uart4_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_1_cts_rts_cfg: uart4-1-cts-rts-cfg { ++ uart4-1-pins { ++ pinmux = , /* uart4_cts */ ++ ; /* uart4_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_2_cfg: uart4-2-cfg { ++ uart4-2-pins { ++ pinmux = , /* uart4_txd */ ++ ; /* uart4_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_3_cfg: uart4-3-cfg { ++ uart4-3-pins { ++ pinmux = , /* uart4_txd */ ++ ; /* uart4_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_3_cts_rts_cfg: uart4-3-cts-rts-cfg { ++ uart4-3-pins { ++ pinmux = , /* uart4_cts */ ++ ; /* uart4_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_4_cfg: uart4-4-cfg { ++ uart4-4-pins { ++ pinmux = , /* uart4_txd */ ++ ; /* uart4_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart4_4_cts_rts_cfg: uart4-4-cts-rts-cfg { ++ uart4-4-pins { ++ pinmux = , /* uart4_cts */ ++ ; /* uart4_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_0_cfg: uart5-0-cfg { ++ uart5-0-pins { ++ pinmux = , /* uart5_txd */ ++ ; /* uart5_rxd */ ++ power-source = <3300>; ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_1_cfg: uart5-1-cfg { ++ uart5-1-pins { ++ pinmux = , /* uart5_txd */ ++ ; /* uart5_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_1_cts_rts_cfg: uart5-1-cts-rts-cfg { ++ uart5-1-pins { ++ pinmux = , /* uart5_cts */ ++ ; /* uart5_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_2_cfg: uart5-2-cfg { ++ uart5-2-pins { ++ pinmux = , /* uart5_txd */ ++ ; /* uart5_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_2_cts_rts_cfg: uart5-2-cts-rts-cfg { ++ uart5-2-pins { ++ pinmux = , /* uart5_cts */ ++ ; /* uart5_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_3_cfg: uart5-3-cfg { ++ uart5-3-pins { ++ pinmux = , /* uart5_txd */ ++ ; /* uart5_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart5_3_cts_rts_cfg: uart5-3-cts-rts-cfg { ++ uart5-3-pins { ++ pinmux = , /* uart5_cts */ ++ ; /* uart5_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6_0_cfg: uart6-0-cfg { ++ uart6-0-pins { ++ pinmux = , /* uart6_txd */ ++ ; /* uart6_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6_0_cts_rts_cfg: uart6-0-cts-rts-cfg { ++ uart6-0-pins { ++ pinmux = , /* uart6_cts */ ++ ; /* uart6_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6_1_cfg: uart6-1-cfg { ++ uart6-1-pins { ++ pinmux = , /* uart6_txd */ ++ ; /* uart6_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6_1_cts_rts_cfg: uart6-1-cts-rts-cfg { ++ uart6-1-pins { ++ pinmux = , /* uart6_cts */ ++ ; /* uart6_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart6_2_cfg: uart6-2-cfg { ++ uart6-2-pins { ++ pinmux = , /* uart6_txd */ ++ ; /* uart6_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7_0_cfg: uart7-0-cfg { ++ uart7-0-pins { ++ pinmux = , /* uart7_txd */ ++ ; /* uart7_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7_1_cfg: uart7-1-cfg { ++ uart7-1-pins { ++ pinmux = , /* uart7_txd */ ++ ; /* uart7_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart7_1_cts_rts_cfg: uart7-1-cts-rts-cfg { ++ uart7-1-pins { ++ pinmux = , /* uart7_cts */ ++ ; /* uart7_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8_0_cfg: uart8-0-cfg { ++ uart8-0-pins { ++ pinmux = , /* uart8_txd */ ++ ; /* uart8_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8_1_cfg: uart8-1-cfg { ++ uart8-1-pins { ++ pinmux = , /* uart8_txd */ ++ ; /* uart8_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8_1_cts_rts_cfg: uart8-1-cts-rts-cfg { ++ uart8-1-pins { ++ pinmux = , /* uart8_cts */ ++ ; /* uart8_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8_2_cfg: uart8-2-cfg { ++ uart8-2-pins { ++ pinmux = , /* uart8_txd */ ++ ; /* uart8_rxd */ ++ power-source = <3300>; ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart8_2_cts_rts_cfg: uart8-2-cts-rts-cfg { ++ uart8-2-pins { ++ pinmux = , /* uart8_cts */ ++ ; /* uart8_rts */ ++ power-source = <3300>; ++ bias-pull-up = <0>; ++ drive-strength = <19>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9_0_cfg: uart9-0-cfg { ++ uart9-0-pins { ++ pinmux = , /* uart9_txd */ ++ ; /* uart9_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9_1_cfg: uart9-1-cfg { ++ uart9-1-pins { ++ pinmux = , /* uart9_txd */ ++ ; /* uart9_rxd */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; ++ ++ /omit-if-no-ref/ ++ uart9_1_cts_rts_cfg: uart9-1-cts-rts-cfg { ++ uart9-1-pins { ++ pinmux = , /* uart9_cts */ ++ ; /* uart9_rts */ ++ bias-pull-up = <0>; ++ drive-strength = <32>; ++ }; ++ }; + ++ /omit-if-no-ref/ ++ uart9_2_cfg: uart9-2-cfg { ++ uart9-2-pins { ++ pinmux = , /* uart9_txd */ ++ ; /* uart9_rxd */ + bias-pull-up = <0>; + drive-strength = <32>; + }; diff --git a/patches/linux/6.18.56/0088-riscv-dts-spacemit-enable-the-i2c8-adapter.patch b/patches/linux/6.18.56/0088-riscv-dts-spacemit-enable-the-i2c8-adapter.patch new file mode 100644 index 0000000000..cdf644c7ad --- /dev/null +++ b/patches/linux/6.18.56/0088-riscv-dts-spacemit-enable-the-i2c8-adapter.patch @@ -0,0 +1,83 @@ +From 068107e84a2ca23f5a3b5f21406dcf42e4ebed8a Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Mon, 25 Aug 2025 12:20:54 -0500 +Subject: [PATCH 088/100] riscv: dts: spacemit: enable the i2c8 adapter + +Define properties for the I2C adapter that provides access to the +SpacemiT P1 PMIC. Enable this adapter on the Banana Pi BPI-F3. + +Signed-off-by: Alex Elder +Link: https://lore.kernel.org/r/20250825172057.163883-6-elder@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 3e8d7309e6260b1d066e733bf3e2e1b6a0d3f82b) +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++++ + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 7 +++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++++++++ + 3 files changed, 32 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index b2c40bae6094..a3644606d8b6 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -92,6 +92,18 @@ &pdma { + status = "okay"; + }; + ++&i2c8 { ++ pinctrl-0 = <&i2c8_cfg>; ++ pinctrl-names = "default"; ++ status = "okay"; ++ ++ pmic@41 { ++ compatible = "spacemit,p1"; ++ reg = <0x41>; ++ interrupts = <64>; ++ }; ++}; ++ + &uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_2_cfg>; +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index 09a4f1dca4f1..7c87811b3ecd 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -75,6 +75,13 @@ gmac1-clk-ref-pins { + }; + }; + ++ i2c8_cfg: i2c8-cfg { ++ i2c8-0-pins { ++ pinmux = , /* PWR_SCL */ ++ ; /* PWR_SDA */ ++ }; ++ }; ++ + /omit-if-no-ref/ + uart0_0_cfg: uart0-0-cfg { + uart0-0-pins { +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 6cdcd80a7c83..3de35077731c 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -459,6 +459,19 @@ pwm7: pwm@d401bc00 { + status = "disabled"; + }; + ++ i2c8: i2c@d401d800 { ++ compatible = "spacemit,k1-i2c"; ++ reg = <0x0 0xd401d800 0x0 0x38>; ++ #address-cells = <1>; ++ #size-cells = <0>; ++ clocks = <&syscon_apbc CLK_TWSI8>, ++ <&syscon_apbc CLK_TWSI8_BUS>; ++ clock-names = "func", "bus"; ++ clock-frequency = <400000>; ++ interrupts = <19>; ++ status = "disabled"; ++ }; ++ + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; + reg = <0x0 0xd401e000 0x0 0x400>; diff --git a/patches/linux/6.18.56/0089-riscv-dts-spacemit-define-fixed-regulators.patch b/patches/linux/6.18.56/0089-riscv-dts-spacemit-define-fixed-regulators.patch new file mode 100644 index 0000000000..90ebf139be --- /dev/null +++ b/patches/linux/6.18.56/0089-riscv-dts-spacemit-define-fixed-regulators.patch @@ -0,0 +1,46 @@ +From 043fcd090f07cc71f957fd928f37687674d928eb Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Mon, 25 Aug 2025 12:20:55 -0500 +Subject: [PATCH 089/100] riscv: dts: spacemit: define fixed regulators + +Define the DC power input and the 4v power as fixed supplies in the +Banana Pi BPI-F3. + +Signed-off-by: Alex Elder +Link: https://lore.kernel.org/r/20250825172057.163883-7-elder@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 1df07a40453fd652132051419140950d47941fe9) +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 19 +++++++++++++++++++ + 1 file changed, 19 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index a3644606d8b6..db73207d9c27 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -30,6 +30,25 @@ led1 { + default-state = "on"; + }; + }; ++ ++ reg_dc_in: dc-in-12v { ++ compatible = "regulator-fixed"; ++ regulator-name = "dc_in_12v"; ++ regulator-min-microvolt = <12000000>; ++ regulator-max-microvolt = <12000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ }; ++ ++ reg_vcc_4v: vcc-4v { ++ compatible = "regulator-fixed"; ++ regulator-name = "vcc_4v"; ++ regulator-min-microvolt = <4000000>; ++ regulator-max-microvolt = <4000000>; ++ regulator-boot-on; ++ regulator-always-on; ++ vin-supply = <®_dc_in>; ++ }; + }; + + &emmc { diff --git a/patches/linux/6.18.56/0090-riscv-dts-spacemit-define-regulator-constraints.patch b/patches/linux/6.18.56/0090-riscv-dts-spacemit-define-regulator-constraints.patch new file mode 100644 index 0000000000..bf82c8bfa4 --- /dev/null +++ b/patches/linux/6.18.56/0090-riscv-dts-spacemit-define-regulator-constraints.patch @@ -0,0 +1,131 @@ +From cacb7418c46d57155175e52b436805fed4aa20bb Mon Sep 17 00:00:00 2001 +From: Alex Elder +Date: Mon, 25 Aug 2025 12:20:56 -0500 +Subject: [PATCH 090/100] riscv: dts: spacemit: define regulator constraints + +Define basic constraints for the regulators in the SpacemiT P1 PMIC, +as implemented in the Banana Pi BPI-F3. + +Signed-off-by: Alex Elder +Link: https://lore.kernel.org/r/20250825172057.163883-8-elder@riscstar.com +Signed-off-by: Yixun Lan +(cherry picked from commit 09a412d397484e76588707d85ccc37f71e491091) +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 104 ++++++++++++++++++ + 1 file changed, 104 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index db73207d9c27..371ce71a4985 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -120,6 +120,110 @@ pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; ++ vin-supply = <®_vcc_4v>; ++ ++ regulators { ++ buck1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <1800000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3300000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ buck6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3450000>; ++ regulator-ramp-delay = <5000>; ++ regulator-always-on; ++ }; ++ ++ aldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ aldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ aldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo1 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-boot-on; ++ }; ++ ++ dldo2 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo3 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo4 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo5 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ ++ dldo6 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ regulator-always-on; ++ }; ++ ++ dldo7 { ++ regulator-min-microvolt = <500000>; ++ regulator-max-microvolt = <3400000>; ++ }; ++ }; + }; + }; + diff --git a/patches/linux/6.18.56/0091-riscv-dts-spacemit-pinctrl-update-register-and-IO-po.patch b/patches/linux/6.18.56/0091-riscv-dts-spacemit-pinctrl-update-register-and-IO-po.patch new file mode 100644 index 0000000000..228495b685 --- /dev/null +++ b/patches/linux/6.18.56/0091-riscv-dts-spacemit-pinctrl-update-register-and-IO-po.patch @@ -0,0 +1,44 @@ +From 5bae9efff65c6f9dc84e4fbd2fa791e390faa782 Mon Sep 17 00:00:00 2001 +From: Troy Mitchell +Date: Thu, 8 Jan 2026 14:42:40 +0800 +Subject: [PATCH 091/100] riscv: dts: spacemit: pinctrl: update register and IO + power + +Change the size of the reg register to 0x1000 to match the hardware. +This register range covers the IO power domain's register addresses. + +The IO power domain registers are protected. In order to access the +protected IO power domain registers, a valid unlock sequence must be +performed by writing the required keys to the AIB Secure Access Register +(ASAR). + +The ASAR register resides within the APBC register address space. +A corresponding syscon property `spacemit,apbc` is added to allow +the pinctrl driver to access this register. + +Signed-off-by: Troy Mitchell +Acked-by: Linus Walleij +Link: https://lore.kernel.org/r/20260108-kx-pinctrl-aib-io-pwr-domain-v2-3-6bcb46146e53@linux.spacemit.com +Signed-off-by: Yixun Lan +(cherry picked from commit 4083d8d6c0aa445fc440d70a5258351c47547ee2) +--- + arch/riscv/boot/dts/spacemit/k1.dtsi | 3 ++- + 1 file changed, 2 insertions(+), 1 deletion(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 3de35077731c..9c13e4dc9f3c 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -474,10 +474,11 @@ i2c8: i2c@d401d800 { + + pinctrl: pinctrl@d401e000 { + compatible = "spacemit,k1-pinctrl"; +- reg = <0x0 0xd401e000 0x0 0x400>; ++ reg = <0x0 0xd401e000 0x0 0x1000>; + clocks = <&syscon_apbc CLK_AIB>, + <&syscon_apbc CLK_AIB_BUS>; + clock-names = "func", "bus"; ++ spacemit,apbc = <&syscon_apbc>; + }; + + pwm8: pwm@d4020000 { diff --git a/patches/linux/6.18.56/0092-riscv-dts-spacemit-Update-PMIC-supply-properties-for.patch b/patches/linux/6.18.56/0092-riscv-dts-spacemit-Update-PMIC-supply-properties-for.patch new file mode 100644 index 0000000000..06df3aec18 --- /dev/null +++ b/patches/linux/6.18.56/0092-riscv-dts-spacemit-Update-PMIC-supply-properties-for.patch @@ -0,0 +1,49 @@ +From c43dadfab8e147e016d5d3cd72ee91c23971e2cb Mon Sep 17 00:00:00 2001 +From: Guodong Xu +Date: Fri, 6 Feb 2026 10:32:04 +0800 +Subject: [PATCH 092/100] riscv: dts: spacemit: Update PMIC supply properties + for BPI-F3 and Jupiter + +Use per-regulator supply names in pmic "spacemit,p1" node to specify +each board's power tree topology and match the updated dt-binding. + +Signed-off-by: Guodong Xu +Reviewed-by: Alex Elder +Link: https://lore.kernel.org/r/20260206-spacemit-p1-v4-3-8f695d93811e@riscstar.com +Signed-off-by: Yixun Lan +[ backport: Jupiter hunks dropped, its 6.18 DT lacks the PMIC node ] +(cherry picked from commit 108c77b34b929e6bdb7ac9613ed65c90da8bcb9f) +--- + arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts | 12 ++++++++++-- + 1 file changed, 10 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index 371ce71a4985..a1ba3f212690 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -120,7 +120,15 @@ pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; +- vin-supply = <®_vcc_4v>; ++ vin1-supply = <®_vcc_4v>; ++ vin2-supply = <®_vcc_4v>; ++ vin3-supply = <®_vcc_4v>; ++ vin4-supply = <®_vcc_4v>; ++ vin5-supply = <®_vcc_4v>; ++ vin6-supply = <®_vcc_4v>; ++ aldoin-supply = <®_vcc_4v>; ++ dldoin1-supply = <&buck5>; ++ dldoin2-supply = <&buck5>; + + regulators { + buck1 { +@@ -151,7 +159,7 @@ buck4 { + regulator-always-on; + }; + +- buck5 { ++ buck5: buck5 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; diff --git a/patches/linux/6.18.56/0093-riscv-dts-spacemit-k1-add-SD-card-controller-and-pin.patch b/patches/linux/6.18.56/0093-riscv-dts-spacemit-k1-add-SD-card-controller-and-pin.patch new file mode 100644 index 0000000000..ad0433648a --- /dev/null +++ b/patches/linux/6.18.56/0093-riscv-dts-spacemit-k1-add-SD-card-controller-and-pin.patch @@ -0,0 +1,104 @@ +From fb3def3a2d5dc721fe67dbc409f7a447217e8b43 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:48:59 +0200 +Subject: [PATCH 093/100] riscv: dts: spacemit: k1: add SD card controller and + pinctrl support + +Add SD card controller infrastructure for SpacemiT K1 SoC with complete +pinctrl support for both standard and UHS modes. + +- Add sdhci0 controller definition with clocks, resets and interrupts +- Add mmc1_cfg pinctrl for 3.3V standard SD operation +- Add mmc1_uhs_cfg pinctrl for 1.8V UHS high-speed operation +- Configure appropriate drive strength and power-source properties + +This provides complete SD card infrastructure that K1-based boards can +enable. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Reviewed-by: Troy Mitchell +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-1-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +[ backport: only sdhci0 and the mmc1 pin groups, the USB3 and SSP3 nodes it was diffed against are not in 6.18 ] +(cherry picked from commit 2d77e577109967ef65f269c1fc1d6a659d4260fb) +--- + arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi | 40 ++++++++++++++++++++ + arch/riscv/boot/dts/spacemit/k1.dtsi | 13 +++++++ + 2 files changed, 53 insertions(+) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +index 7c87811b3ecd..ce76b1243d29 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1-pinctrl.dtsi +@@ -525,4 +525,44 @@ pwm14-1-pins { + drive-strength = <32>; + }; + }; ++ ++ mmc1_cfg: mmc1-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <19>; ++ power-source = <3300>; ++ }; ++ }; ++ ++ mmc1_uhs_cfg: mmc1-uhs-cfg { ++ mmc1-data-cmd-pins { ++ pinmux = , /* mmc1_d3 */ ++ , /* mmc1_d2 */ ++ , /* mmc1_d1 */ ++ , /* mmc1_d0 */ ++ ; /* mmc1_cmd */ ++ bias-pull-up = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ ++ mmc1-clk-pins { ++ pinmux = ; /* mmc1_clk */ ++ bias-pull-down = <1>; ++ drive-strength = <42>; ++ power-source = <1800>; ++ }; ++ }; + }; +diff --git a/arch/riscv/boot/dts/spacemit/k1.dtsi b/arch/riscv/boot/dts/spacemit/k1.dtsi +index 9c13e4dc9f3c..2adc11153b3b 100644 +--- a/arch/riscv/boot/dts/spacemit/k1.dtsi ++++ b/arch/riscv/boot/dts/spacemit/k1.dtsi +@@ -870,6 +870,19 @@ storage-bus { + #size-cells = <2>; + dma-ranges = <0x0 0x00000000 0x0 0x00000000 0x0 0x80000000>; + ++ sdhci0: mmc@d4280000 { ++ compatible = "spacemit,k1-sdhci"; ++ reg = <0x0 0xd4280000 0x0 0x200>; ++ clocks = <&syscon_apmu CLK_SDH_AXI>, ++ <&syscon_apmu CLK_SDH0>; ++ clock-names = "core", "io"; ++ resets = <&syscon_apmu RESET_SDH_AXI>, ++ <&syscon_apmu RESET_SDH0>; ++ reset-names = "axi", "sdh"; ++ interrupts = <99>; ++ status = "disabled"; ++ }; ++ + emmc: mmc@d4281000 { + compatible = "spacemit,k1-sdhci"; + reg = <0x0 0xd4281000 0x0 0x200>; diff --git a/patches/linux/6.18.56/0094-riscv-dts-spacemit-k1-bananapi-f3-add-SD-card-suppor.patch b/patches/linux/6.18.56/0094-riscv-dts-spacemit-k1-bananapi-f3-add-SD-card-suppor.patch new file mode 100644 index 0000000000..d703bb84ae --- /dev/null +++ b/patches/linux/6.18.56/0094-riscv-dts-spacemit-k1-bananapi-f3-add-SD-card-suppor.patch @@ -0,0 +1,88 @@ +From a0b9436be9e9d76155b95a1142d3b1f5dbbf13de Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Fri, 15 May 2026 12:49:01 +0200 +Subject: [PATCH 094/100] riscv: dts: spacemit: k1-bananapi-f3: add SD card + support with UHS modes + +Add complete SD card controller support with UHS high-speed modes. + +- Enable sdhci0 controller with 4-bit bus width +- Configure card detect GPIO with GPIO_ACTIVE_LOW and internal pull-up + support +- Connect vmmc-supply to buck4 for 3.3V card power +- Connect vqmmc-supply to aldo1 for 1.8V/3.3V I/O switching +- Add dual pinctrl states for voltage-dependent pin configuration +- Support UHS-I SDR25, SDR50, and SDR104 modes +- Add stable MMC device aliases (mmc0 = eMMC, mmc1 = SD card) + +This enables full SD card functionality including high-speed UHS modes +for improved performance. + +Suggested-by: Anand Moon +Tested-by: Anand Moon +Tested-by: Margherita Milani +Tested-by: Aurelien Jarno +Reviewed-by: Aurelien Jarno +Signed-off-by: Iker Pedrosa +Link: https://patch.msgid.link/20260515-orangepi-sd-card-uhs-v10-3-094af27e310d@gmail.com +Signed-off-by: Yixun Lan +[ backport: only the sdhci0 node and its aliases, USB3 hub and SPI parts dropped ] +(cherry picked from commit c76e2f058cbcab84e4a703f26857a58bdf6a0042) +--- + .../boot/dts/spacemit/k1-bananapi-f3.dts | 25 +++++++++++++++++-- + 1 file changed, 23 insertions(+), 2 deletions(-) + +diff --git a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +index a1ba3f212690..a9588f3a3dbe 100644 +--- a/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts ++++ b/arch/riscv/boot/dts/spacemit/k1-bananapi-f3.dts +@@ -14,6 +14,9 @@ aliases { + ethernet0 = ð0; + ethernet1 = ð1; + serial0 = &uart0; ++ i2c8 = &i2c8; ++ mmc0 = &emmc; ++ mmc1 = &sdhci0; + }; + + chosen { +@@ -152,7 +155,7 @@ buck3 { + regulator-always-on; + }; + +- buck4 { ++ buck4: buck4 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-ramp-delay = <5000>; +@@ -173,7 +176,7 @@ buck6 { + regulator-always-on; + }; + +- aldo1 { ++ aldo1: aldo1 { + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; +@@ -240,3 +243,21 @@ &uart0 { + pinctrl-0 = <&uart0_2_cfg>; + status = "okay"; + }; ++ ++&sdhci0 { ++ pinctrl-names = "default", "uhs"; ++ pinctrl-0 = <&mmc1_cfg>; ++ pinctrl-1 = <&mmc1_uhs_cfg>; ++ bus-width = <4>; ++ cd-gpios = <&gpio K1_GPIO(80) (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; ++ no-mmc; ++ no-sdio; ++ disable-wp; ++ cap-sd-highspeed; ++ vmmc-supply = <&buck4>; ++ vqmmc-supply = <&aldo1>; ++ sd-uhs-sdr25; ++ sd-uhs-sdr50; ++ sd-uhs-sdr104; ++ status = "okay"; ++}; diff --git a/patches/linux/6.18.56/0095-mmc-sdhci-of-k1-add-reset-support.patch b/patches/linux/6.18.56/0095-mmc-sdhci-of-k1-add-reset-support.patch new file mode 100644 index 0000000000..051786143d --- /dev/null +++ b/patches/linux/6.18.56/0095-mmc-sdhci-of-k1-add-reset-support.patch @@ -0,0 +1,63 @@ +From 561c4dc54c3d6401b4f34b80c4425da589d1b6c1 Mon Sep 17 00:00:00 2001 +From: Yixun Lan +Date: Tue, 23 Dec 2025 10:24:50 +0800 +Subject: [PATCH 095/100] mmc: sdhci-of-k1: add reset support + +The SDHCI controller of SpacemiT K1 SoC requires two resets, add +support to explicitly request the reset line and deassert during +initialization phase. Still using devm_xx_get_optional() API to +make the request optional. + +Signed-off-by: Yixun Lan +Reviewed-by: Javier Martinez Canillas +Signed-off-by: Ulf Hansson +(cherry picked from commit 658b716c048684ad13d78280d69b883f181251da) +--- + drivers/mmc/host/sdhci-of-k1.c | 20 ++++++++++++++++++++ + 1 file changed, 20 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 0cc97e23a2f9..a160e1d5d9bd 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -15,6 +15,7 @@ + #include + #include + #include ++#include + #include + + #include "sdhci.h" +@@ -223,6 +224,21 @@ static inline int spacemit_sdhci_get_clocks(struct device *dev, + return 0; + } + ++static inline int spacemit_sdhci_get_resets(struct device *dev) ++{ ++ struct reset_control *rst; ++ ++ rst = devm_reset_control_get_optional_shared_deasserted(dev, "axi"); ++ if (IS_ERR(rst)) ++ return PTR_ERR(rst); ++ ++ rst = devm_reset_control_get_optional_exclusive_deasserted(dev, "sdh"); ++ if (IS_ERR(rst)) ++ return PTR_ERR(rst); ++ ++ return 0; ++} ++ + static const struct sdhci_ops spacemit_sdhci_ops = { + .get_max_clock = spacemit_sdhci_clk_get_max_clock, + .reset = spacemit_sdhci_reset, +@@ -284,6 +300,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + if (ret) + goto err_pltfm; + ++ ret = spacemit_sdhci_get_resets(dev); ++ if (ret) ++ goto err_pltfm; ++ + ret = sdhci_add_host(host); + if (ret) + goto err_pltfm; diff --git a/patches/linux/6.18.56/0096-mmc-sdhci-of-k1-enable-essential-clock-infrastructur.patch b/patches/linux/6.18.56/0096-mmc-sdhci-of-k1-enable-essential-clock-infrastructur.patch new file mode 100644 index 0000000000..7b0c87e9fe --- /dev/null +++ b/patches/linux/6.18.56/0096-mmc-sdhci-of-k1-enable-essential-clock-infrastructur.patch @@ -0,0 +1,62 @@ +From 9dcad57290c8f0268b7d4f7ab544a33d2a92514f Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:57 +0200 +Subject: [PATCH 096/100] mmc: sdhci-of-k1: enable essential clock + infrastructure for SD operation + +Ensure SD card pins receive clock signals by enabling pad clock +generation and overriding automatic clock gating. Required for all SD +operation modes. + +The SDHC_GEN_PAD_CLK_ON setting in LEGACY_CTRL_REG is safe for both SD +and eMMC operation as both protocols use the same physical MMC interface +pins and require proper clock signal generation at the hardware level +for signal integrity and timing. + +Additional SD-specific clock overrides (SDHC_OVRRD_CLK_OEN and +SDHC_FORCE_CLK_ON) are conditionally applied only for SD-only +controllers to handle removable card scenarios. + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit f87b273e4b6dfe57dcd63c24cbe3764d1f6954ae) +--- + drivers/mmc/host/sdhci-of-k1.c | 13 +++++++++++++ + 1 file changed, 13 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index a160e1d5d9bd..76f4799c6491 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -21,6 +21,13 @@ + #include "sdhci.h" + #include "sdhci-pltfm.h" + ++#define SPACEMIT_SDHC_OP_EXT_REG 0x108 ++#define SDHC_OVRRD_CLK_OEN BIT(11) ++#define SDHC_FORCE_CLK_ON BIT(12) ++ ++#define SPACEMIT_SDHC_LEGACY_CTRL_REG 0x10C ++#define SDHC_GEN_PAD_CLK_ON BIT(6) ++ + #define SPACEMIT_SDHC_MMC_CTRL_REG 0x114 + #define SDHC_MISC_INT_EN BIT(1) + #define SDHC_MISC_INT BIT(2) +@@ -101,6 +108,12 @@ static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + + if (!(host->mmc->caps2 & MMC_CAP2_NO_MMC)) + spacemit_sdhci_setbits(host, SDHC_MMC_CARD_MODE, SPACEMIT_SDHC_MMC_CTRL_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_GEN_PAD_CLK_ON, SPACEMIT_SDHC_LEGACY_CTRL_REG); ++ ++ if (host->mmc->caps2 & MMC_CAP2_NO_MMC) ++ spacemit_sdhci_setbits(host, SDHC_OVRRD_CLK_OEN | SDHC_FORCE_CLK_ON, ++ SPACEMIT_SDHC_OP_EXT_REG); + } + + static void spacemit_sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned int timing) diff --git a/patches/linux/6.18.56/0097-mmc-sdhci-of-k1-add-regulator-and-pinctrl-voltage-sw.patch b/patches/linux/6.18.56/0097-mmc-sdhci-of-k1-add-regulator-and-pinctrl-voltage-sw.patch new file mode 100644 index 0000000000..16d146fbf0 --- /dev/null +++ b/patches/linux/6.18.56/0097-mmc-sdhci-of-k1-add-regulator-and-pinctrl-voltage-sw.patch @@ -0,0 +1,141 @@ +From ed58a909842615d15ac19a341fd83c20ba405205 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:58 +0200 +Subject: [PATCH 097/100] mmc: sdhci-of-k1: add regulator and pinctrl voltage + switching support + +Add voltage switching infrastructure for UHS-I modes by integrating both +regulator framework (for supply voltage control) and pinctrl state +switching (for pin drive strength optimization). + +- Add regulator supply parsing and voltage switching callback +- Add optional pinctrl state switching between "default" (3.3V) and + "state_uhs" (1.8V) configurations +- Enable coordinated voltage and pin configuration changes for UHS modes + +This provides complete voltage switching support while maintaining +backward compatibility when pinctrl states are not defined. + +Tested-by: Anand Moon +Tested-by: Trevor Gamblin +Acked-by: Adrian Hunter +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit 00a97fc57c09ff1cf71107753d9b5629caeb8c8a) +--- + drivers/mmc/host/sdhci-of-k1.c | 72 ++++++++++++++++++++++++++++++++++ + 1 file changed, 72 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 76f4799c6491..6b01ac7ebf58 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -16,6 +16,7 @@ + #include + #include + #include ++#include + #include + + #include "sdhci.h" +@@ -71,6 +72,9 @@ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; ++ struct pinctrl *pinctrl; ++ struct pinctrl_state *pinctrl_default; ++ struct pinctrl_state *pinctrl_uhs; + }; + + /* All helper functions will update clr/set while preserve rest bits */ +@@ -219,6 +223,46 @@ static void spacemit_sdhci_pre_hs400_to_hs200(struct mmc_host *mmc) + SPACEMIT_SDHC_PHY_CTRL_REG); + } + ++static int spacemit_sdhci_start_signal_voltage_switch(struct mmc_host *mmc, ++ struct mmc_ios *ios) ++{ ++ struct sdhci_host *host = mmc_priv(mmc); ++ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ struct pinctrl_state *state; ++ int ret; ++ ++ ret = sdhci_start_signal_voltage_switch(mmc, ios); ++ if (ret) ++ return ret; ++ ++ if (!sdhst->pinctrl) ++ return 0; ++ ++ /* Select appropriate pinctrl state based on signal voltage */ ++ switch (ios->signal_voltage) { ++ case MMC_SIGNAL_VOLTAGE_330: ++ state = sdhst->pinctrl_default; ++ break; ++ case MMC_SIGNAL_VOLTAGE_180: ++ state = sdhst->pinctrl_uhs; ++ break; ++ default: ++ dev_warn(mmc_dev(mmc), "unsupported voltage %d\n", ios->signal_voltage); ++ return 0; ++ } ++ ++ ret = pinctrl_select_state(sdhst->pinctrl, state); ++ if (ret) { ++ dev_warn(mmc_dev(mmc), "failed to select pinctrl state: %d\n", ret); ++ return 0; ++ } ++ dev_dbg(mmc_dev(mmc), "switched to %s pinctrl state\n", ++ ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180 ? "UHS" : "default"); ++ ++ return 0; ++} ++ + static inline int spacemit_sdhci_get_clocks(struct device *dev, + struct sdhci_pltfm_host *pltfm_host) + { +@@ -252,6 +296,30 @@ static inline int spacemit_sdhci_get_resets(struct device *dev) + return 0; + } + ++static inline void spacemit_sdhci_get_pins(struct device *dev, ++ struct sdhci_pltfm_host *pltfm_host) ++{ ++ struct spacemit_sdhci_host *sdhst = sdhci_pltfm_priv(pltfm_host); ++ ++ sdhst->pinctrl = devm_pinctrl_get(dev); ++ if (IS_ERR(sdhst->pinctrl)) { ++ sdhst->pinctrl = NULL; ++ dev_dbg(dev, "pinctrl not available, voltage switching will work without it\n"); ++ return; ++ } ++ ++ sdhst->pinctrl_default = pinctrl_lookup_state(sdhst->pinctrl, "default"); ++ if (IS_ERR(sdhst->pinctrl_default)) ++ sdhst->pinctrl_default = NULL; ++ ++ sdhst->pinctrl_uhs = pinctrl_lookup_state(sdhst->pinctrl, "uhs"); ++ if (IS_ERR(sdhst->pinctrl_uhs)) ++ sdhst->pinctrl_uhs = NULL; ++ ++ dev_dbg(dev, "pinctrl setup: default=%p, uhs=%p\n", ++ sdhst->pinctrl_default, sdhst->pinctrl_uhs); ++} ++ + static const struct sdhci_ops spacemit_sdhci_ops = { + .get_max_clock = spacemit_sdhci_clk_get_max_clock, + .reset = spacemit_sdhci_reset, +@@ -309,6 +377,10 @@ static int spacemit_sdhci_probe(struct platform_device *pdev) + + host->mmc->caps |= MMC_CAP_NEED_RSP_BUSY; + ++ spacemit_sdhci_get_pins(dev, pltfm_host); ++ ++ host->mmc_host_ops.start_signal_voltage_switch = spacemit_sdhci_start_signal_voltage_switch; ++ + ret = spacemit_sdhci_get_clocks(dev, pltfm_host); + if (ret) + goto err_pltfm; diff --git a/patches/linux/6.18.56/0098-mmc-sdhci-of-k1-add-comprehensive-SDR-tuning-support.patch b/patches/linux/6.18.56/0098-mmc-sdhci-of-k1-add-comprehensive-SDR-tuning-support.patch new file mode 100644 index 0000000000..21aaa7c63a --- /dev/null +++ b/patches/linux/6.18.56/0098-mmc-sdhci-of-k1-add-comprehensive-SDR-tuning-support.patch @@ -0,0 +1,238 @@ +From ee33c390956dce5ac9602c904b44df030bf4ba11 Mon Sep 17 00:00:00 2001 +From: Iker Pedrosa +Date: Mon, 11 May 2026 10:53:59 +0200 +Subject: [PATCH 098/100] mmc: sdhci-of-k1: add comprehensive SDR tuning + support +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +Implement software tuning algorithm to enable UHS-I SDR modes for SD +card operation and HS200 mode for eMMC. This adds both TX and RX delay +line tuning based on the SpacemiT K1 controller capabilities. + +Algorithm features: +- Add tuning register definitions (RX_CFG, DLINE_CTRL, DLINE_CFG) +- Conditional tuning: only for high-speed modes (≥100MHz) +- TX tuning: configure transmit delay line with optimal values + (dline_reg=0, delaycode=127) to ensure optimal signal output timing +- RX tuning: single-pass window detection algorithm testing full + delay range (0-255) to find optimal receive timing window +- Retry mechanism: multiple fallback delays within optimal window + for improved reliability + +Tested-by: Anand Moon +Acked-by: Adrian Hunter +Tested-by: Trevor Gamblin +Tested-by: Vincent Legoll +Signed-off-by: Iker Pedrosa +Signed-off-by: Ulf Hansson +(cherry picked from commit e9cb83c10071808aa7db4582e007a650aa6aa183) +--- + drivers/mmc/host/sdhci-of-k1.c | 172 +++++++++++++++++++++++++++++++++ + 1 file changed, 172 insertions(+) + +diff --git a/drivers/mmc/host/sdhci-of-k1.c b/drivers/mmc/host/sdhci-of-k1.c +index 6b01ac7ebf58..bbad58c6e729 100644 +--- a/drivers/mmc/host/sdhci-of-k1.c ++++ b/drivers/mmc/host/sdhci-of-k1.c +@@ -69,6 +69,28 @@ + #define SDHC_PHY_DRIVE_SEL GENMASK(2, 0) + #define SDHC_RX_BIAS_CTRL BIT(5) + ++#define SPACEMIT_SDHC_RX_CFG_REG 0x118 ++#define SDHC_RX_SDCLK_SEL0_MASK GENMASK(1, 0) ++#define SDHC_RX_SDCLK_SEL1_MASK GENMASK(3, 2) ++#define SDHC_RX_SDCLK_SEL1 FIELD_PREP(SDHC_RX_SDCLK_SEL1_MASK, 1) ++ ++#define SPACEMIT_SDHC_DLINE_CTRL_REG 0x130 ++#define SDHC_DLINE_PU BIT(0) ++#define SDHC_RX_DLINE_CODE_MASK GENMASK(23, 16) ++#define SDHC_TX_DLINE_CODE_MASK GENMASK(31, 24) ++ ++#define SPACEMIT_SDHC_DLINE_CFG_REG 0x134 ++#define SDHC_RX_DLINE_REG_MASK GENMASK(7, 0) ++#define SDHC_RX_DLINE_GAIN BIT(8) ++#define SDHC_TX_DLINE_REG_MASK GENMASK(23, 16) ++ ++#define SPACEMIT_RX_DLINE_REG 9 ++#define SPACEMIT_RX_TUNE_DELAY_MIN 0x0 ++#define SPACEMIT_RX_TUNE_DELAY_MAX 0xFF ++ ++#define SPACEMIT_TX_TUNING_DLINE_REG 0x00 ++#define SPACEMIT_TX_TUNING_DELAYCODE 127 ++ + struct spacemit_sdhci_host { + struct clk *clk_core; + struct clk *clk_io; +@@ -96,6 +118,50 @@ static inline void spacemit_sdhci_clrsetbits(struct sdhci_host *host, u32 clr, u + sdhci_writel(host, val, reg); + } + ++static void spacemit_sdhci_set_rx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_delay(struct sdhci_host *host, u8 delay) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_CODE_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_CODE_MASK, delay), ++ SPACEMIT_SDHC_DLINE_CTRL_REG); ++} ++ ++static void spacemit_sdhci_set_tx_dline_reg(struct sdhci_host *host, u8 dline_reg) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_TX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_TX_DLINE_REG_MASK, dline_reg), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++} ++ ++static void spacemit_sdhci_tx_tuning_prepare(struct sdhci_host *host) ++{ ++ spacemit_sdhci_setbits(host, SDHC_TX_MUX_SEL, SPACEMIT_SDHC_TX_CFG_REG); ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++} ++ ++static void spacemit_sdhci_prepare_tuning(struct sdhci_host *host) ++{ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_DLINE_REG_MASK, ++ FIELD_PREP(SDHC_RX_DLINE_REG_MASK, SPACEMIT_RX_DLINE_REG), ++ SPACEMIT_SDHC_DLINE_CFG_REG); ++ ++ spacemit_sdhci_setbits(host, SDHC_DLINE_PU, SPACEMIT_SDHC_DLINE_CTRL_REG); ++ udelay(5); ++ ++ spacemit_sdhci_clrsetbits(host, SDHC_RX_SDCLK_SEL1_MASK, SDHC_RX_SDCLK_SEL1, ++ SPACEMIT_SDHC_RX_CFG_REG); ++ ++ if (host->mmc->ios.timing == MMC_TIMING_MMC_HS200) ++ spacemit_sdhci_setbits(host, SDHC_HS200_USE_RFIFO, SPACEMIT_SDHC_PHY_FUNC_REG); ++} ++ + static void spacemit_sdhci_reset(struct sdhci_host *host, u8 mask) + { + sdhci_reset(host, mask); +@@ -191,6 +257,111 @@ static unsigned int spacemit_sdhci_clk_get_max_clock(struct sdhci_host *host) + return clk_get_rate(pltfm_host->clk); + } + ++static int spacemit_sdhci_execute_tuning(struct sdhci_host *host, u32 opcode) ++{ ++ int current_len = 0, current_start = 0; ++ int max_pass_len = 0, max_pass_start = 0; ++ struct mmc_host *mmc = host->mmc; ++ struct mmc_ios ios = mmc->ios; ++ u8 final_delay; ++ int ret = 0; ++ int i; ++ ++ /* ++ * Tuning is required for SDR50/SDR104, HS200/HS400 cards and ++ * if clock frequency is greater than 100MHz in these modes. ++ */ ++ if (host->clock < 100 * 1000 * 1000 || ++ !(ios.timing == MMC_TIMING_MMC_HS200 || ++ ios.timing == MMC_TIMING_UHS_SDR50 || ++ ios.timing == MMC_TIMING_UHS_SDR104)) ++ return 0; ++ ++ if (mmc->caps2 & MMC_CAP2_NO_MMC) { ++ spacemit_sdhci_set_tx_dline_reg(host, SPACEMIT_TX_TUNING_DLINE_REG); ++ spacemit_sdhci_set_tx_delay(host, SPACEMIT_TX_TUNING_DELAYCODE); ++ spacemit_sdhci_tx_tuning_prepare(host); ++ ++ dev_dbg(mmc_dev(host->mmc), "TX tuning: dline_reg=%d, delaycode=%d\n", ++ SPACEMIT_TX_TUNING_DLINE_REG, SPACEMIT_TX_TUNING_DELAYCODE); ++ } ++ ++ spacemit_sdhci_prepare_tuning(host); ++ ++ for (i = SPACEMIT_RX_TUNE_DELAY_MIN; i <= SPACEMIT_RX_TUNE_DELAY_MAX; i++) { ++ spacemit_sdhci_set_rx_delay(host, i); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ ++ dev_dbg(mmc_dev(host->mmc), "RX delay %d: %s\n", ++ i, ret == 0 ? "pass" : "fail"); ++ ++ if (ret == 0) { ++ /* Test passed - extend current window */ ++ if (current_len == 0) ++ current_start = i; ++ current_len++; ++ } else { ++ /* Test failed - check if current window is best so far */ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ current_len = 0; ++ } ++ } ++ ++ if (current_len > max_pass_len) { ++ max_pass_len = current_len; ++ max_pass_start = current_start; ++ } ++ ++ if (max_pass_len < 3) { ++ dev_err(mmc_dev(host->mmc), "Tuning failed: no stable window found\n"); ++ return -EIO; ++ } ++ ++ final_delay = max_pass_start + max_pass_len / 2; ++ spacemit_sdhci_set_rx_delay(host, final_delay); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (ret) { ++ u8 retry_delays[] = { ++ max_pass_start + max_pass_len / 4, ++ max_pass_start + (3 * max_pass_len) / 4, ++ max_pass_start, ++ max_pass_start + max_pass_len - 1 ++ }; ++ int retry_count = ARRAY_SIZE(retry_delays); ++ ++ dev_warn(mmc_dev(mmc), "Primary delay %d failed, trying alternatives\n", ++ final_delay); ++ ++ for (i = 0; i < retry_count; i++) { ++ if (retry_delays[i] >= SPACEMIT_RX_TUNE_DELAY_MIN && ++ retry_delays[i] <= SPACEMIT_RX_TUNE_DELAY_MAX) { ++ spacemit_sdhci_set_rx_delay(host, retry_delays[i]); ++ ret = mmc_send_tuning(host->mmc, opcode, NULL); ++ if (!ret) { ++ final_delay = retry_delays[i]; ++ dev_info(mmc_dev(mmc), "Retry successful with delay %d\n", ++ final_delay); ++ break; ++ } ++ } ++ } ++ ++ if (ret) { ++ dev_err(mmc_dev(mmc), "All retry attempts failed\n"); ++ return -EIO; ++ } ++ } ++ ++ dev_dbg(mmc_dev(host->mmc), ++ "Tuning successful: window %d-%d, using delay %d\n", ++ max_pass_start, max_pass_start + max_pass_len - 1, final_delay); ++ ++ return 0; ++} ++ + static int spacemit_sdhci_pre_select_hs400(struct mmc_host *mmc) + { + struct sdhci_host *host = mmc_priv(mmc); +@@ -326,6 +497,7 @@ static const struct sdhci_ops spacemit_sdhci_ops = { + .set_bus_width = sdhci_set_bus_width, + .set_clock = spacemit_sdhci_set_clock, + .set_uhs_signaling = spacemit_sdhci_set_uhs_signaling, ++ .platform_execute_tuning = spacemit_sdhci_execute_tuning, + }; + + static const struct sdhci_pltfm_data spacemit_sdhci_k1_pdata = { diff --git a/patches/linux/6.18.56/0099-driver-reset-spacemit-p1-add-driver-for-poweroff-reb.patch b/patches/linux/6.18.56/0099-driver-reset-spacemit-p1-add-driver-for-poweroff-reb.patch new file mode 100644 index 0000000000..7211f638fb --- /dev/null +++ b/patches/linux/6.18.56/0099-driver-reset-spacemit-p1-add-driver-for-poweroff-reb.patch @@ -0,0 +1,151 @@ +From 33784f1f5221651440a3043d41ed314b9263d9d4 Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Mon, 3 Nov 2025 00:01:59 +0100 +Subject: [PATCH 099/100] driver: reset: spacemit-p1: add driver for + poweroff/reboot + +This driver implements poweroff/reboot support for the SpacemiT P1 PMIC +chip, which is commonly paired with the SpacemiT K1 SoC. + +The SpacemiT P1 support is implemented as a MFD driver, so the access is +done directly through the regmap interface. Reboot or poweroff is +triggered by setting a specific bit in a control register, which is +automatically cleared by the hardware afterwards. + +Signed-off-by: Aurelien Jarno +Link: https://patch.msgid.link/20251102230352.914421-2-aurelien@aurel32.net +Signed-off-by: Sebastian Reichel +(cherry picked from commit 28124cc0fb8c7dc01a6834d227351e25d9a92c58) +--- + drivers/power/reset/Kconfig | 9 +++ + drivers/power/reset/Makefile | 1 + + drivers/power/reset/spacemit-p1-reboot.c | 88 ++++++++++++++++++++++++ + 3 files changed, 98 insertions(+) + create mode 100644 drivers/power/reset/spacemit-p1-reboot.c + +diff --git a/drivers/power/reset/Kconfig b/drivers/power/reset/Kconfig +index 8248895ca903..f6c1bcbb57de 100644 +--- a/drivers/power/reset/Kconfig ++++ b/drivers/power/reset/Kconfig +@@ -283,6 +283,15 @@ config POWER_RESET_KEYSTONE + help + Reboot support for the KEYSTONE SoCs. + ++config POWER_RESET_SPACEMIT_P1 ++ tristate "SpacemiT P1 poweroff and reset driver" ++ depends on ARCH_SPACEMIT || COMPILE_TEST ++ depends on MFD_SPACEMIT_P1 ++ default MFD_SPACEMIT_P1 ++ help ++ This driver supports power-off and reset operations for the SpacemiT ++ P1 PMIC. ++ + config POWER_RESET_SYSCON + bool "Generic SYSCON regmap reset driver" + depends on OF +diff --git a/drivers/power/reset/Makefile b/drivers/power/reset/Makefile +index 51da87e05ce7..0e4ae6f6b5c5 100644 +--- a/drivers/power/reset/Makefile ++++ b/drivers/power/reset/Makefile +@@ -24,6 +24,7 @@ obj-$(CONFIG_POWER_RESET_LTC2952) += ltc2952-poweroff.o + obj-$(CONFIG_POWER_RESET_QNAP) += qnap-poweroff.o + obj-$(CONFIG_POWER_RESET_REGULATOR) += regulator-poweroff.o + obj-$(CONFIG_POWER_RESET_RESTART) += restart-poweroff.o ++obj-$(CONFIG_POWER_RESET_SPACEMIT_P1) += spacemit-p1-reboot.o + obj-$(CONFIG_POWER_RESET_ST) += st-poweroff.o + obj-$(CONFIG_POWER_RESET_TH1520_AON) += th1520-aon-reboot.o + obj-$(CONFIG_POWER_RESET_TORADEX_EC) += tdx-ec-poweroff.o +diff --git a/drivers/power/reset/spacemit-p1-reboot.c b/drivers/power/reset/spacemit-p1-reboot.c +new file mode 100644 +index 000000000000..9ec3d1fff8f3 +--- /dev/null ++++ b/drivers/power/reset/spacemit-p1-reboot.c +@@ -0,0 +1,88 @@ ++// SPDX-License-Identifier: GPL-2.0 ++/* ++ * Copyright (C) 2025 by Aurelien Jarno ++ */ ++ ++#include ++#include ++#include ++#include ++#include ++ ++/* Power Control Register 2 */ ++#define PWR_CTRL2 0x7e ++#define PWR_CTRL2_SHUTDOWN BIT(2) /* Shutdown request */ ++#define PWR_CTRL2_RST BIT(1) /* Reset request */ ++ ++static int spacemit_p1_pwroff_handler(struct sys_off_data *data) ++{ ++ struct regmap *regmap = data->cb_data; ++ int ret; ++ ++ /* Put the PMIC into shutdown state */ ++ ret = regmap_set_bits(regmap, PWR_CTRL2, PWR_CTRL2_SHUTDOWN); ++ if (ret) { ++ dev_err(data->dev, "shutdown failed: %d\n", ret); ++ return notifier_from_errno(ret); ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++static int spacemit_p1_restart_handler(struct sys_off_data *data) ++{ ++ struct regmap *regmap = data->cb_data; ++ int ret; ++ ++ /* Put the PMIC into reset state */ ++ ret = regmap_set_bits(regmap, PWR_CTRL2, PWR_CTRL2_RST); ++ if (ret) { ++ dev_err(data->dev, "restart failed: %d\n", ret); ++ return notifier_from_errno(ret); ++ } ++ ++ return NOTIFY_DONE; ++} ++ ++static int spacemit_p1_reboot_probe(struct platform_device *pdev) ++{ ++ struct device *dev = &pdev->dev; ++ struct regmap *regmap; ++ int ret; ++ ++ regmap = dev_get_regmap(dev->parent, NULL); ++ if (!regmap) ++ return -ENODEV; ++ ++ ret = devm_register_power_off_handler(dev, &spacemit_p1_pwroff_handler, ++ regmap); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Failed to register power off handler\n"); ++ ++ ret = devm_register_restart_handler(dev, spacemit_p1_restart_handler, ++ regmap); ++ if (ret) ++ return dev_err_probe(dev, ret, ++ "Failed to register restart handler\n"); ++ ++ return 0; ++} ++ ++static const struct platform_device_id spacemit_p1_reboot_id_table[] = { ++ { "spacemit-p1-reboot", }, ++ { /* sentinel */ }, ++}; ++MODULE_DEVICE_TABLE(platform, spacemit_p1_reboot_id_table); ++ ++static struct platform_driver spacemit_p1_reboot_driver = { ++ .driver = { ++ .name = "spacemit-p1-reboot", ++ }, ++ .probe = spacemit_p1_reboot_probe, ++ .id_table = spacemit_p1_reboot_id_table, ++}; ++module_platform_driver(spacemit_p1_reboot_driver); ++ ++MODULE_DESCRIPTION("SpacemiT P1 reboot/poweroff driver"); ++MODULE_LICENSE("GPL"); diff --git a/patches/linux/6.18.56/0100-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-the-Spacemi.patch b/patches/linux/6.18.56/0100-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-the-Spacemi.patch new file mode 100644 index 0000000000..69da4414f4 --- /dev/null +++ b/patches/linux/6.18.56/0100-mfd-simple-mfd-i2c-Add-a-reboot-cell-for-the-Spacemi.patch @@ -0,0 +1,30 @@ +From 19c5b3dcf894c3ef73dd6304aa8758b16121b5ad Mon Sep 17 00:00:00 2001 +From: Aurelien Jarno +Date: Mon, 3 Nov 2025 00:02:00 +0100 +Subject: [PATCH 100/100] mfd: simple-mfd-i2c: Add a reboot cell for the + SpacemiT P1 chip + +Add a "spacemit-p1-reboot" cell for the SpacemiT P1 chip. + +Signed-off-by: Aurelien Jarno +Reviewed-by: Troy Mitchell +Tested-by: Vincent Legoll # OrangePi-RV2 +Link: https://patch.msgid.link/20251102230352.914421-3-aurelien@aurel32.net +Signed-off-by: Lee Jones +(cherry picked from commit 25c80f08e54ef5298eb68866f755f35b59a26d2b) +--- + drivers/mfd/simple-mfd-i2c.c | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/drivers/mfd/simple-mfd-i2c.c b/drivers/mfd/simple-mfd-i2c.c +index 9f911afafc25..c4166e8aeb9d 100644 +--- a/drivers/mfd/simple-mfd-i2c.c ++++ b/drivers/mfd/simple-mfd-i2c.c +@@ -99,6 +99,7 @@ static const struct regmap_config spacemit_p1_regmap_config = { + }; + + static const struct mfd_cell spacemit_p1_cells[] = { ++ { .name = "spacemit-p1-reboot", }, + { .name = "spacemit-p1-regulator", }, + { .name = "spacemit-p1-rtc", }, + }; diff --git a/patches/opensbi/opensbi.hash b/patches/opensbi/opensbi.hash index bc4058abe6..4b171576fd 100644 --- a/patches/opensbi/opensbi.hash +++ b/patches/opensbi/opensbi.hash @@ -1,2 +1,3 @@ # Locally calculated sha256 319b62a4186fbce9b81a0c5f0ec9f003a10c808397a72138bc9745d9b87b1eb1 opensbi-1.4.tar.gz +sha256 fb1ae61a85e966322101acb1c982f84d9eaafc4de7dd474a7d7546d9bb321c6f opensbi-1.8.1.tar.gz diff --git a/utils/mkimage.sh b/utils/mkimage.sh index c942744e93..0e59aa0130 100755 --- a/utils/mkimage.sh +++ b/utils/mkimage.sh @@ -185,6 +185,9 @@ get_bootloader_name() acer-connect-vero-w6m) echo "bpi_r3_emmc_boot" ;; + bananapi-bpi-f3) + echo "bpi_f3_boot" + ;; bananapi-bpi-m1) echo "bpi_m1_boot" ;; @@ -222,6 +225,9 @@ get_bootloader_name() novarq-tactical-1000) echo "tactical_boot" ;; + starfive-visionfive2) + echo "visionfive2_boot" + ;; *) err "Unknown bootloader for board: $board" return 1