diff --git a/NVL/events/novalake_arcticwolf_core.json b/NVL/events/novalake_arcticwolf_core.json
index 7e40a24d..13057778 100644
--- a/NVL/events/novalake_arcticwolf_core.json
+++ b/NVL/events/novalake_arcticwolf_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.03",
-    "DatePublished": "08/28/2026",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04",
+    "DatePublished": "08/31/2026",
+    "Version": "1.04",
     "Legend": ""
   },
   "Events": [
@@ -6648,6 +6648,35 @@
       "ProgrammingRestriction": "None",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xcd",
+      "UMask": "0x01",
+      "UMaskExt": "0x00",
+      "EventName": "ARITH.IDIV_ACTIVE",
+      "BriefDescription": "Counts the number of cycles when any of the integer dividers are active.",
+      "PublicDescription": "Counts the number of cycles when any of the integer dividers are active.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offmodule": "0",
+      "Deprecated": "0",
+      "Equal": "0",
+      "PDISTCounter": "NA",
+      "CounterType": "PGMABLE",
+      "ProgrammingRestriction": "None",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xcd",
       "UMask": "0x02",
@@ -6706,6 +6735,35 @@
       "ProgrammingRestriction": "None",
       "Speculative": "1"
     },
+    {
+      "EventCode": "0xcd",
+      "UMask": "0x03",
+      "UMaskExt": "0x00",
+      "EventName": "ARITH.DIV_ACTIVE",
+      "BriefDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.",
+      "PublicDescription": "Counts the number of cycles when any of the floating point or integer dividers are active.",
+      "Counter": "0,1,2,3,4,5,6,7",
+      "PEBScounters": "0,1,2,3,4,5,6,7",
+      "SampleAfterValue": "1000003",
+      "MSRIndex": "0x00",
+      "MSRValue": "0x00",
+      "Precise": "0",
+      "CollectPEBSRecord": "2",
+      "TakenAlone": "0",
+      "CounterMask": "1",
+      "Invert": "0",
+      "EdgeDetect": "0",
+      "Data_LA": "0",
+      "L1_Hit_Indication": "0",
+      "Errata": "null",
+      "Offmodule": "0",
+      "Deprecated": "0",
+      "Equal": "0",
+      "PDISTCounter": "NA",
+      "CounterType": "PGMABLE",
+      "ProgrammingRestriction": "None",
+      "Speculative": "1"
+    },
     {
       "EventCode": "0xcd",
       "UMask": "0x04",
diff --git a/NVL/events/novalake_coyotecove_core.json b/NVL/events/novalake_coyotecove_core.json
index b90d9097..2eb453c9 100644
--- a/NVL/events/novalake_coyotecove_core.json
+++ b/NVL/events/novalake_coyotecove_core.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.03",
-    "DatePublished": "08/28/2026",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04",
+    "DatePublished": "08/31/2026",
+    "Version": "1.04",
     "Legend": ""
   },
   "Events": [
diff --git a/NVL/events/novalake_uncore.json b/NVL/events/novalake_uncore.json
index 39ed6e01..881ca7f1 100644
--- a/NVL/events/novalake_uncore.json
+++ b/NVL/events/novalake_uncore.json
@@ -1,9 +1,9 @@
 {
   "Header": {
     "Copyright": "Copyright (c) 2001 - 2026 Intel Corporation. All rights reserved.",
-    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.03",
-    "DatePublished": "08/28/2026",
-    "Version": "1.03",
+    "Info": "Performance Monitoring Events for Intel(R) Core(TM) Processor - V1.04",
+    "DatePublished": "08/31/2026",
+    "Version": "1.04",
     "Legend": ""
   },
   "Events": [
diff --git a/mapfile.csv b/mapfile.csv
index 451b5a5d..dad1b255 100644
--- a/mapfile.csv
+++ b/mapfile.csv
@@ -250,9 +250,9 @@ GenuineIntel-6-DD,V1.04,/CWF/events/clearwaterforest_core.json,core,,,
 GenuineIntel-6-DD,V1.04,/CWF/events/clearwaterforest_uncore.json,uncore,,,
 GenuineIntel-6-DD,V1.04,/CWF/events/clearwaterforest_uncore_experimental.json,uncore experimental,,,
 GenuineIntel-6-DD,V1.0,/CWF/metrics/clearwaterforest_metrics.json,metrics,,,
-GenuineIntel-18-1,V1.03,/NVL/events/novalake_arcticwolf_core.json,hybridcore,0x20,0x000005,Atom
-GenuineIntel-18-1,V1.03,/NVL/events/novalake_coyotecove_core.json,hybridcore,0x40,0x000005,Core
-GenuineIntel-18-1,V1.03,/NVL/events/novalake_uncore.json,uncore,,,
-GenuineIntel-18-3,V1.03,/NVL/events/novalake_arcticwolf_core.json,hybridcore,0x20,0x000005,Atom
-GenuineIntel-18-3,V1.03,/NVL/events/novalake_coyotecove_core.json,hybridcore,0x40,0x000005,Core
-GenuineIntel-18-3,V1.03,/NVL/events/novalake_uncore.json,uncore,,,
+GenuineIntel-18-1,V1.04,/NVL/events/novalake_arcticwolf_core.json,hybridcore,0x20,0x000005,Atom
+GenuineIntel-18-1,V1.04,/NVL/events/novalake_coyotecove_core.json,hybridcore,0x40,0x000005,Core
+GenuineIntel-18-1,V1.04,/NVL/events/novalake_uncore.json,uncore,,,
+GenuineIntel-18-3,V1.04,/NVL/events/novalake_arcticwolf_core.json,hybridcore,0x20,0x000005,Atom
+GenuineIntel-18-3,V1.04,/NVL/events/novalake_coyotecove_core.json,hybridcore,0x40,0x000005,Core
+GenuineIntel-18-3,V1.04,/NVL/events/novalake_uncore.json,uncore,,,