From 803556e7eb4c0ec83968030163566aa3becf1fc8 Mon Sep 17 00:00:00 2001 From: JiTianYu391 Date: Sat, 17 Oct 2026 17:02:31 +0800 Subject: [PATCH 1/3] usb: ehci: fix the USBCMD and PORTSC bit definitions Two groups of EHCI register bits did not match EHCI 1.0 (sections 2.3.1 and 2.3.9) or Linux's include/linux/usb/ehci_def.h: USBCMD ASE bit 2 -> bit 5 (bits 3:2 are Frame List Size) PSE bit 3 -> bit 4 PORTSC CSC bit 17 -> bit 1 (bits 19:16 are Port Test Control) PED bit 1 -> bit 2 PEC bit 18 -> bit 3 Together they kept every EHCI device from enumerating: - After the port reset, ehci_port_reset() tested "PED" but read CSC, which the worker had already cleared, so a high-speed device looked not enabled and the port was handed to the companion (-ENODEV). - With that fixed, "ASE" landed in the Frame List Size field, which QEMU rejects ("attempt to set frame list size"), so the async schedule never started and the first SET_ADDRESS timed out (-ETIMEDOUT). Tested in QEMU (q35, usb-ehci + usb-storage): before, "usb-ehci: Port 0 enumeration failed: -19" and no /dev/sda; with only the PORTSC fix, -110; with both, /dev/sda appears. Signed-off-by: JiTianYu391 Co-Authored-By: Claude Opus 5.5 --- include/drivers/usb/host/ehci/ehci.h | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/include/drivers/usb/host/ehci/ehci.h b/include/drivers/usb/host/ehci/ehci.h index 2b637315..0218acef 100644 --- a/include/drivers/usb/host/ehci/ehci.h +++ b/include/drivers/usb/host/ehci/ehci.h @@ -38,8 +38,8 @@ /* USBCMD bits */ #define EHCI_CMD_RUN (1U << 0) #define EHCI_CMD_HCRESET (1U << 1) -#define EHCI_CMD_ASENE (1U << 2) -#define EHCI_CMD_PSEN (1U << 3) +#define EHCI_CMD_PSEN (1U << 4) +#define EHCI_CMD_ASENE (1U << 5) #define EHCI_CMD_IAAD (1U << 6) #define EHCI_CMD_LRESET (1U << 7) #define EHCI_CMD_ASYNC (1U << 8) @@ -63,7 +63,9 @@ /* PORTSC bits */ #define EHCI_PORT_CCS (1U << 0) -#define EHCI_PORT_PED (1U << 1) +#define EHCI_PORT_CSC (1U << 1) +#define EHCI_PORT_PED (1U << 2) +#define EHCI_PORT_PEC (1U << 3) #define EHCI_PORT_PR (1U << 8) #define EHCI_PORT_PP (1U << 12) #define EHCI_PORT_PO (1U << 13) @@ -74,8 +76,6 @@ #define EHCI_PORT_PTC_MASK (0x0fU << 3) /* Bits 26-27 are controller-specific on some implementations; do not use them to infer speed on a standards-compliant EHCI controller. */ -#define EHCI_PORT_CSC (1U << 17) -#define EHCI_PORT_PEC (1U << 18) #define EHCI_PORT_CHANGE_BITS (EHCI_PORT_CSC | EHCI_PORT_PEC) /* HCSPARAMS bits */ From 198a39cd85a263e6af5228537bc725e8bc244ccc Mon Sep 17 00:00:00 2001 From: MicroFish <2609948707@qq.com> Date: Tue, 20 Oct 2026 23:52:18 +0800 Subject: [PATCH 2/3] usb: ehci: fix the remaining register bit definitions EHCI_CMD_ASYNC was defined at USBCMD bit 8, but bits 9:8 are the park mode count and the park enable is bit 11. Replace it with the park count field and EHCI_CMD_PARK. EHCI_PORT_PTC_SHIFT pointed at bits 6:3 instead of the port test control field at bits 19:16, so it overlapped PEC, OCA, OCC and FPR. The QH endpoint-capability block defined C at bits 1:0 and RL at bits 7:4. Neither field exists there: C is the control endpoint flag at bit 27 (already covered by EHCI_QH_CONTROL) and RL is the NAK counter reload at bits 31:28. Drop the bogus pair and give RL its real field. EHCI_HCS_NCC and EHCI_HCS_NPCC were named the wrong way round: bits 11:8 are N_PCC and bits 15:12 are N_CC. None of the corrected macros had users, so no generated code changes. Signed-off-by: MicroFish <2609948707@qq.com> Co-Authored-By: Claude Code --- include/drivers/usb/host/ehci/ehci.h | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/include/drivers/usb/host/ehci/ehci.h b/include/drivers/usb/host/ehci/ehci.h index 0218acef..63828079 100644 --- a/include/drivers/usb/host/ehci/ehci.h +++ b/include/drivers/usb/host/ehci/ehci.h @@ -42,7 +42,9 @@ #define EHCI_CMD_ASENE (1U << 5) #define EHCI_CMD_IAAD (1U << 6) #define EHCI_CMD_LRESET (1U << 7) -#define EHCI_CMD_ASYNC (1U << 8) +#define EHCI_CMD_PARK_CNT_SHIFT 8 +#define EHCI_CMD_PARK_CNT_MASK (3U << 8) +#define EHCI_CMD_PARK (1U << 11) /* USBSTS bits */ #define EHCI_STS_INT (1U << 0) @@ -72,8 +74,8 @@ #define EHCI_PORT_LS_SHIFT 10 #define EHCI_PORT_LS_MASK (3U << 10) #define EHCI_PORT_LS_KSTATE (1U << 10) -#define EHCI_PORT_PTC_SHIFT 3 -#define EHCI_PORT_PTC_MASK (0x0fU << 3) +#define EHCI_PORT_PTC_SHIFT 16 +#define EHCI_PORT_PTC_MASK (0x0fU << 16) /* Bits 26-27 are controller-specific on some implementations; do not use them to infer speed on a standards-compliant EHCI controller. */ #define EHCI_PORT_CHANGE_BITS (EHCI_PORT_CSC | EHCI_PORT_PEC) @@ -82,10 +84,10 @@ #define EHCI_HCS_PORTS_SHIFT 0 #define EHCI_HCS_PORTS_MASK (0x0fU << 0) #define EHCI_HCS_PPC (1U << 4) -#define EHCI_HCS_NCC_SHIFT 8 -#define EHCI_HCS_NCC_MASK (0x0fU << 8) -#define EHCI_HCS_NPCC_SHIFT 12 -#define EHCI_HCS_NPCC_MASK (0x0fU << 12) +#define EHCI_HCS_NPCC_SHIFT 8 +#define EHCI_HCS_NPCC_MASK (0x0fU << 8) +#define EHCI_HCS_NCC_SHIFT 12 +#define EHCI_HCS_NCC_MASK (0x0fU << 12) /* HCCPARAMS bits */ #define EHCI_HCC_PFL (1U << 0) @@ -108,13 +110,10 @@ #define EHCI_QH_MPL_SHIFT 16 #define EHCI_QH_MPL_MASK (0x07ffU << 16) #define EHCI_QH_CONTROL (1U << 27) -#define EHCI_QH_NRTL (1U << 28) +#define EHCI_QH_RL_SHIFT 28 +#define EHCI_QH_RL_MASK (0x0fU << 28) /* QH endpoint capability bits */ -#define EHCI_QH_C_SHIFT 0 -#define EHCI_QH_C_MASK (3U << 0) -#define EHCI_QH_RL_SHIFT 4 -#define EHCI_QH_RL_MASK (0x0fU << 4) #define EHCI_QH_MUL_SHIFT 30 #define EHCI_QH_MUL_MASK (3U << 30) From c3ea2b2e48e41330be9e559be6592780e9d2c99b Mon Sep 17 00:00:00 2001 From: MicroFish <2609948707@qq.com> Date: Wed, 21 Oct 2026 00:05:13 +0800 Subject: [PATCH 3/3] usb: ehci: align the USBCMD macro definitions clang-format lines up the USBCMD macros with the longer park count field added by the previous change. Signed-off-by: MicroFish <2609948707@qq.com> --- include/drivers/usb/host/ehci/ehci.h | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/include/drivers/usb/host/ehci/ehci.h b/include/drivers/usb/host/ehci/ehci.h index 63828079..7e18d396 100644 --- a/include/drivers/usb/host/ehci/ehci.h +++ b/include/drivers/usb/host/ehci/ehci.h @@ -36,15 +36,15 @@ #define EHCI_PORT_STRIDE 4 /* USBCMD bits */ -#define EHCI_CMD_RUN (1U << 0) -#define EHCI_CMD_HCRESET (1U << 1) -#define EHCI_CMD_PSEN (1U << 4) -#define EHCI_CMD_ASENE (1U << 5) -#define EHCI_CMD_IAAD (1U << 6) -#define EHCI_CMD_LRESET (1U << 7) +#define EHCI_CMD_RUN (1U << 0) +#define EHCI_CMD_HCRESET (1U << 1) +#define EHCI_CMD_PSEN (1U << 4) +#define EHCI_CMD_ASENE (1U << 5) +#define EHCI_CMD_IAAD (1U << 6) +#define EHCI_CMD_LRESET (1U << 7) #define EHCI_CMD_PARK_CNT_SHIFT 8 #define EHCI_CMD_PARK_CNT_MASK (3U << 8) -#define EHCI_CMD_PARK (1U << 11) +#define EHCI_CMD_PARK (1U << 11) /* USBSTS bits */ #define EHCI_STS_INT (1U << 0)