diff --git a/com.minres.coredsl/src/com/minres/coredsl/CoreDsl.xtext b/com.minres.coredsl/src/com/minres/coredsl/CoreDsl.xtext
index 847938f..8bfe2ec 100644
--- a/com.minres.coredsl/src/com/minres/coredsl/CoreDsl.xtext
+++ b/com.minres.coredsl/src/com/minres/coredsl/CoreDsl.xtext
@@ -91,17 +91,17 @@ ReturnStatement: {ReturnStatement} t_return='return' value=ConditionalExpression
 LoopStatement: WhileLoop | ForLoop | DoLoop;
 
 WhileLoop:
-	'while' '(' condition=Expression ')' body=Statement;
+	'while' '(' condition=Expression ')' attributes+=Attribute* body=Statement;
 
 ForLoop:
 	'for' '('
 	(startDeclaration=MultiInitDeclaration | startExpression=AssignmentExpression?) ';'
 	(condition=Expression?) ';'
 	(loopExpressions+=AssignmentExpression (',' loopExpressions+=AssignmentExpression)*)?
-	')' body=Statement;
+	')' attributes+=Attribute* body=Statement;
 
 DoLoop:
-	'do' body=Statement 'while' '(' condition=Expression ')' ';';
+	'do' body=Statement 'while' '(' condition=Expression ')' attributes+=Attribute* ';';
 
 //////////////////////////////////////////////////////////////////////////////
 //////////////////////////////// Declarations ////////////////////////////////
diff --git a/com.minres.coredsl/src/com/minres/coredsl/analysis/AttributeRegistry.xtend b/com.minres.coredsl/src/com/minres/coredsl/analysis/AttributeRegistry.xtend
index b73b9cd..e66d7bb 100644
--- a/com.minres.coredsl/src/com/minres/coredsl/analysis/AttributeRegistry.xtend
+++ b/com.minres.coredsl/src/com/minres/coredsl/analysis/AttributeRegistry.xtend
@@ -35,7 +35,8 @@ class AttributeRegistry {
 		instruction,
 		function,
 		declarator,
-		alwaysBlock
+		alwaysBlock,
+		loop
 	}
 
 	static final class AttributeInfo {
diff --git a/com.minres.coredsl/src/com/minres/coredsl/analysis/CoreDslAnalyzer.xtend b/com.minres.coredsl/src/com/minres/coredsl/analysis/CoreDslAnalyzer.xtend
index a231a2d..33fcf91 100644
--- a/com.minres.coredsl/src/com/minres/coredsl/analysis/CoreDslAnalyzer.xtend
+++ b/com.minres.coredsl/src/com/minres/coredsl/analysis/CoreDslAnalyzer.xtend
@@ -581,6 +581,9 @@ class CoreDslAnalyzer {
      * 2. [Warning] The condition should not be an assignment. <i>(LikelyAccidentalAssignment)</i>
      */
     def static dispatch void analyzeStatement(AnalysisContext ctx, WhileLoop statement) {
+
+        analyzeAttributes(ctx, statement.attributes, AttributeRegistry.AttributeUsage.loop);
+
         val conditionType = analyzeExpression(ctx, statement.condition);
 
         checkAccidentalAssignment(ctx, statement.condition);
@@ -601,6 +604,8 @@ class CoreDslAnalyzer {
      */
     def static dispatch void analyzeStatement(AnalysisContext ctx, ForLoop statement) {
 
+        analyzeAttributes(ctx, statement.attributes, AttributeRegistry.AttributeUsage.loop);
+
         if (statement.startDeclaration !== null) {
             analyzeDeclaration(ctx, statement.startDeclaration, false);
         }
@@ -641,6 +646,9 @@ class CoreDslAnalyzer {
      * 2. [Warning] The condition should not be an assignment. <i>(LikelyAccidentalAssignment)</i>
      */
     def static dispatch void analyzeStatement(AnalysisContext ctx, DoLoop statement) {
+
+        analyzeAttributes(ctx, statement.attributes, AttributeRegistry.AttributeUsage.loop);
+
         val conditionType = analyzeExpression(ctx, statement.condition);
 
         checkAccidentalAssignment(ctx, statement.condition);