[TLOAD] ColMajor global tensor Vec lowering emits NORM without a representable column stride

[jiale-wangOwO]

Summary

The TileOP API CPU/reference backend supports arbitrary 2-D global-tensor strides, including ColMajor<Rows, Cols> with index = column * ColStride + row. The accelerator lowering for a Vec TLOAD, however, still emits the PTO v0.58 NORM form and carries only one B.IOR stride value. This loses the GM column stride/layout and produces an ELF whose architectural semantics do not match the API expectation.

This was reported as SuperScalarModel#273.

Minimal reproducer

For ColMajor<8,32>:

for (int j = 0; j < 32; ++j)
    for (int i = 0; i < 8; ++i)
        mem[j * 8 + i] = static_cast<float>(i * 100 + j);

using gm = global_tensor<float, ColMajor<8, 32>>;
using tile = Tile<Location::Vec, float, 8, 32, BLayout::ColMajor>;
TLOAD(tile, gm(mem));

The API expectation is:

tile[i][j] = mem[j * 8 + i]

with row 0 equal to [0, 1, 2, 3, 4, 5, 6, 7].

The reported accelerator run produces 248/256 mismatches, while the equivalent RowMajor case passes.

Architectural contract

The current PTO ASL defines TLOAD GM addressing as:

base + (row * row_stride_elements + column) * element_size

B.IOR source 0 is the GM base and source 1 is the logical row stride. There is no independent column-stride operand in the v0.58 TLOAD contract.

References:

• TileMemoryStridedIndex
• TLOAD memory semantics
• TLOAD GM address contract
• B.IOR source binding

Root cause

The API exposes a richer ColMajor semantic at the host/reference level, but the Vec accelerator path selects NORM. NORM makes the second logical coordinate contiguous; it cannot express column * ColStride + row for a general ColMajor GM. Encoding only a row stride, or swapping dimensions without a formally defined contract, is not sufficient to make the emitted instruction semantically ColMajor.

This is not a gfrun-only issue. gfrun and QEMU both implement the current ASL NORM formula, so changing gfrun to infer ColMajor from a stride value or a layout heuristic would break ASL and cross-model parity.

Expected resolution

Please choose and document one architectural lowering strategy:

1. Lower supported ColMajor Vec transfers to an ASL-defined DN form, with the GM-side layout and dimension mapping explicitly specified and tested; or
2. Extend PTO/its contract with an explicit GM column stride or 2-D stride, then update ASL, compiler, gfrun, QEMU, and cross-model tests; or
3. Reject unsupported direct ColMajor Vec TLOAD at compile time or lower it to a sequence whose semantics are already expressible by the current ISA.

Please add an accelerator regression test that compares the generated ELF semantics against the CPU/reference ColMajor result. An ELF/disassembly for SuperScalarModel#273 would also help confirm the exact B.DATR, LB0/LB1/LB2, and B.IOR fields.

[zhoubot]

2026-08-21 normative stride update

PTO-SPEC PR #117 has now resolved the row-stride unit: explicit B.IOR RegSrc1 for TLOAD/TSTORE is bytes.

Current API remains internally inconsistent:

• TLoadBackend.hpp/TStoreBackend.hpp convert tensor stride to bytes.
• the one-layer template_asm.hpp TLOAD/TSTORE overloads pass GetStride(3) directly and describe it as a logical row stride.

This affects RowMajor tensors as well as the ColMajor representability problem already tracked here. Please add a RowMajor FP16/FP32 non-dense stride test that checks both disassembly and result memory, and make all API surfaces use byte stride before closing.